# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = C:\work\ISE\c11SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Complex_Multiplier family Xilinx,_Inc. 2.1# END Select# BEGIN ParametersCSET b_width=16CSET a_width=16CSET pipe_in=falseCSET p_width=16CSET optimize=Number_Of_xTremeDSP_Slice_UsedCSET component_name=complex_multCSET pipe_out=trueCSET round=Truncate_ResultsCSET sclr=falseCSET pipe_mid=true# END ParametersGENERATE