LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST IS
PORT(CLK1HZ:IN STD_LOGIC;
     FSIN:IN STD_LOGIC;
     DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END FREQTEST;
ARCHITECTURE STRUC OF FREQTEST IS
COMPONENT FTCTRL
PORT(CLKK:IN STD_LOGIC;
   CNT_EN:OUT STD_LOGIC;
   RST_CNT:OUT STD_LOGIC;
   LOAD:OUT STD_LOGIC);
END COMPONENT;
COMPONENT COUNT16
PORT(FIN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENABL:IN STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT;
COMPONENT REG16
PORT(LK:IN STD_LOGIC;
     DIN:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
     DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT;
SIGNAL TSTEN1:STD_LOGIC;
SIGNAL CLR_CNT1:STD_LOGIC;
SIGNAL LOAD1:STD_LOGIC;
SIGNAL DTO1:STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CARRY_OUT1:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
U1:FTCTRL PORT MAP(CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,LOAD=>LOAD1);
U2:REG16 PORT MAP(LK=>LOAD1,DIN=>DTO1,DOUT=>DOUT);
U3:COUNT16 PORT MAP(FIN=>FSIN,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO1);
END STRUC;
2．底層文件
（1）測頻控制電路
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FTCTRL IS
PORT(CLKK:IN STD_LOGIC;
     CNT_EN:OUT STD_LOGIC;
     RST_CNT:OUT STD_LOGIC;
     LOAD: OUT STD_LOGIC);
END FTCTRL;
ARCHITECTURE BEHAV OF FTCTRL IS
SIGNAL DIV2CLK:STD_LOGIC;
BEGIN
PROCESS(CLKK)
BEGIN
IF CLKK'EVENT AND CLKK='1' THEN
DIV2CLK<=NOT DIV2CLK;
END IF;
END PROCESS;
PROCESS(CLKK,DIV2CLK)
BEGIN
IF CLKK='0' AND DIV2CLK='0' THEN RST_CNT<='1';
ELSE RST_CNT<='0';END IF;
END PROCESS;
LOAD<=NOT DIV2CLK;
CNT_EN<=DIV2CLK;
END BEHAV;
（2）十進制計數器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT16 IS
  PORT(CLR,ENABL,FIN:IN STD_LOGIC;
       DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY;
ARCHITECTURE BEHAVE OF COUNT16 IS
BEGIN
PROCESS(CLR,ENABL,FIN)
VARIABLE GOUT:STD_LOGIC_VECTOR(15 DOWNTO 0);
  BEGIN
 IF (CLR='1') THEN GOUT:=(OTHERS=>'0');
 ELSIF ENABL='1'  THEN
    IF(FIN'EVENT AND FIN='1') THEN
       
       IF GOUT(3 DOWNTO 0)="1001" THEN 
          GOUT(3 DOWNTO 0):="0000";
          GOUT(7 DOWNTO 4):=GOUT(7 DOWNTO 4)+1;
        ELSE GOUT(3 DOWNTO 0):=GOUT (3 DOWNTO 0)+1;
       END IF;
         IF GOUT(7 DOWNTO 4)="1010" THEN
           GOUT(7 DOWNTO 4):="0000";
           GOUT(11 DOWNTO 8):=GOUT(11 DOWNTO 8)+1;
        END IF;
           IF GOUT(11 DOWNTO 8)="1010" THEN
             GOUT(11 DOWNTO 8):="0000" ;
             GOUT(15 DOWNTO 12):=GOUT(15 DOWNTO 12)+1;
        END IF;
       END IF;
       END IF;
DOUT<=GOUT;
END PROCESS;
END BEHAVE;
（3）鎖存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG16 IS
PORT(LK:IN STD_LOGIC;
    DIN:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
   DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END REG16;
ARCHITECTURE BEHAV OF REG16 IS
BEGIN
PROCESS(LK,DIN)
BEGIN
IF LK'EVENT AND LK='1' THEN DOUT<=DIN;
END IF;
END PROCESS;
END BEHAV;