/*******************************************************************************
* COPYRIGHT (C)             中國普天研究院			                           *
********************************************************************************
* 源文件名: BBU_DD_ChipCsl.h                                                   *
* 功能描述：Specific Registers Description for TMS320C6414 and TMS320C6416     *
* 編寫者：louyajun                                                             *
* 版本：1.0.0                                                                  *
* 編制日期：07/19/2004                                                         *
* 說明：                                                                       *
* 修改歷史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* REGISTERS
*
* CSR    - control/status register
* IFR    - interrupt flag register
* ISR    - interrupt set register
* ICR    - interrupt clear register
* IER    - interrupt enable register
* ISTP   - interrupt service table pointer register
* IRP    - interrupt return pointer
* NRP    - non-maskable interrupt return pointer
* AMR    - addressing mode reister


* DIER   - DSP interrupt exception register  (3)not complete
* EM     - exception mask register  (3) not complete
* ER     - exception flag register  (3) not complete
* GFPGFR - Galois field polynomial generator function register  (3)
* (3) only supported on 6414/15/16 devices
*
\******************************************************************************/

#ifndef _BBU_DD_CHIPCSL_H_
#define _BBU_DD_CHIPCSL_H_

#include "BBU_DD_Stdinc.h"

/******************************************************************************\
*              CSR  -  control and status register
*
* CPUID[31:24]    - r,  CPU ID identifies CPUs Type
* REVID[23:16]    - r,  CPU Revision ID                                        
* PWRD[15:10]     - rw, Control power down modes                                       
* SAT[9]          - rc, The saturate bit, set when any unit performs a saturate
* EN[8]           - r,  Endian bit: 1 = little endian, 0 = big endian 
* PCC[7:5]        - rw, Program cache control mode                                      
* DCC[4:2]        - rw, Data cache control mode
* PGIE[1]         - rw, Previous GIE, saves GIE when an interrupt is taken
* GIE[0]          - rw, Global interrupt enable; enables (1) or disables (0) all
*                       interrupts except the reset interrupt and NMI
*       
\******************************************************************************/
extern far cregister volatile Uint32 CSR;

#define CHIP_CSR_DEFAULT            0x00000000u

#define CHIP_CSR_CPUID_MASK         0xFF000000u
#define CHIP_CSR_CPUID_SHIFT        0x00000018u
#define CHIP_CSR_CPUID_DEFAULT      0x00000000u
#define CHIP_CSR_CPUID_C64X         0x0000000Cu 

#define CHIP_CSR_REVID_MASK         0x00FF0000u 
#define CHIP_CSR_REVID_SHIFT        0x00000010u
#define CHIP_CSR_REVID_DEFAULT      0x00000000u
#define CHIP_CSR_REVID_640011       0x00000001u

#define CHIP_CSR_PWRD_MASK          0x0000FC00u
#define CHIP_CSR_PWRD_SHIFT         0x0000000Au
#define CHIP_CSR_PWRD_DEFAULT       0x00000000u
#define CHIP_CSR_PWRD_NONE          0x00000000u

/* In PD1A and PD1B mode, CPU halted (except for the interrupt logic), blocks */
/* the internal clock inputs at the boundary of the CPU, preventing most of   */
/* the CPU’s logic from switching. During PD1, EDMA transactions can proceed  */
/* between peripherals and internal memory                                    */      
#define CHIP_CSR_PWRD_PD1A          0x00000009u /* Wake by an enabled interrup*/
#define CHIP_CSR_PWRD_PD1B          0x00000011u /* Wake by an enabled or
                                                   non-enabled interrupt */                                                                                                  

/* In PD2 mode,Output clock from PLL is halted, stopping the internal clock   */
/* structure from switching and resulting in the entire chip being halted.    */
/* All register and internal RAM contents are preserved. All functional I/O   */
/* freeze in the last state when the PLL clock is turned off                  */                                                  
#define CHIP_CSR_PWRD_PD2           0x0000001Au /* Wake by a device reset */

/* In PD3 mode,Input clock to the PLL stops generating clocks. All register   */
/* and internal RAM contents are preserved. All functional I/O freeze in the  */
/* last state when the PLL clock is turned off. Following reset, the PLL needs*/
/* time to re-lock, just as it does following power-up                        */
#define CHIP_CSR_PWRD_PD3           0x0000001Cu /* Wake by a device reset */

#define CHIP_CSR_SAT_MASK           0x00000200u
#define CHIP_CSR_SAT_SHIFT          0x00000009u
#define CHIP_CSR_SAT_DEFAULT        0x00000000u
#define CHIP_CSR_SAT_0              0x00000000u
#define CHIP_CSR_SAT_1              0x00000001u

#define CHIP_CSR_EN_MASK            0x00000100u
#define CHIP_CSR_EN_SHIFT           0x00000008u
#define CHIP_CSR_EN_DEFAULT         0x00000000u
#define CHIP_CSR_EN_BIG             0x00000000u
#define CHIP_CSR_EN_LITTLE          0x00000001u

#define CHIP_CSR_PCC_MASK           0x000000E0u
#define CHIP_CSR_PCC_SHIFT          0x00000005u
#define CHIP_CSR_PCC_DEFAULT        0x00000000u
#define CHIP_CSR_PCC_MAPPED         0x00000000u
#define CHIP_CSR_PCC_ENABLE         0x00000002u
#define CHIP_CSR_PCC_FREEZE         0x00000003u
#define CHIP_CSR_PCC_BYPASS         0x00000004u

#define CHIP_CSR_DCC_MASK           0x0000001Cu
#define CHIP_CSR_DCC_SHIFT          0x00000002u
#define CHIP_CSR_DCC_DEFAULT        0x00000000u
#define CHIP_CSR_DCC_MAPPED         0x00000000u
#define CHIP_CSR_DCC_ENABLE         0x00000002u
#define CHIP_CSR_DCC_FREEZE         0x00000003u
#define CHIP_CSR_DCC_BYPASS         0x00000004u

#define CHIP_CSR_PGIE_MASK          0x00000002u
#define CHIP_CSR_PGIE_SHIFT         0x00000001u
#define CHIP_CSR_PGIE_DEFAULT       0x00000000u
#define CHIP_CSR_PGIE_0             0x00000000u
#define CHIP_CSR_PGIE_1             0x00000001u

#define CHIP_CSR_GIE_MASK           0x00000001u
#define CHIP_CSR_GIE_SHIFT          0x00000000u
#define CHIP_CSR_GIE_DEFAULT        0x00000000u
#define CHIP_CSR_GIE_0              0x00000000u
#define CHIP_CSR_GIE_1              0x00000001u

/******************************************************************************\
*              IFR  -  interruppt flag register
*
* IF[15:0]   - rw, Each interrupt’s corresponding bit in the IFR is set to 1
*                  when that interrupt occurs; otherwise, the bits have a value
*                  of 0
*       
\******************************************************************************/
extern far cregister volatile Uint32 IFR;

#define CHIP_IFR_DEFAULT            0x00000000u

#define CHIP_IFR_IF_MASK            0x0000FFFFu
#define CHIP_IFR_IF_SHIFT           0x00000000u
#define CHIP_IFR_IF_DEFAULT         0x00000000u

/******************************************************************************\
*              ISR  -  interruppt set register
*
* IS[15:0]    - w, Allow you to set maskable interrupts manually in the IFR. 
*                  Writing a 1 to IS4–IS15 of the ISR causes the corresponding
*                  interrupt flag to be set in the IFR
*       
\******************************************************************************/
extern far cregister volatile unsigned int ISR;

#define CHIP_ISR_DEFAULT            0x00000000u

#define CHIP_ISR_IS_MASK            0x0000FFFFu
#define CHIP_ISR_IS_SHIFT           0x00000000u
#define CHIP_ISR_IS_DEFAULT         0x00000000u

/******************************************************************************\
*              ICR - interruppt clear register
*
* IC[15:0]    - w, Allow you to clear maskable interrupts manually in the IFR. 
*                  Writing a 1 to IC4–IC15 of the ICR causes the corresponding
*                  interrupt flag to be cleared in the IFR
*       
\******************************************************************************/
extern far cregister volatile Uint32 ICR;

#define CHIP_ICR_DEFAULT            0x00000000u

#define CHIP_ICR_IC_MASK            0x0000FFFFu
#define CHIP_ICR_IC_SHIFT           0x00000000u
#define CHIP_ICR_IC_DEFAULT         0x00000000u

/******************************************************************************\
*              IER - interruppt enable register
*
* IE[15:0]  - rw, You can enable and disable individual interrupts by setting
*                 and clearing bits in the IER that correspond to the individual
*                 interrupts. An interrupt can trigger interrupt processing only
*                 if the corresponding bit in the IER is set. 
*                 Bit 0, corresponding to reset, is not writeable and is always
*                 read as 1, so the reset interrupt is always enabled.
*                 Bits IE4–IE15 can be written as 1 or 0, enabling or disabling
*                 the associated interrupt, respectively.
*
\******************************************************************************/
extern far cregister volatile Uint32 IER;

#define CHIP_IER_DEFAULT            0x00000001u
  
#define CHIP_IER_IE_MASK            0x0000FFFFu
#define CHIP_IER_IE_SHIFT           0x00000000u
#define CHIP_IER_IE_DEFAULT         0x00000000u

/******************************************************************************\
*              ISTP - interrupt service table pointer register
*
* ISTB[31:10]     - rw, Identifies the base portion of the address of the IST
* HPEINT[9:5]     - r,  highest priority enabled interrupt 
*
\******************************************************************************/
extern far cregister volatile Uint32 ISTP;

#define CHIP_ISTP_DEFAULT           0x00000000u
    
#define CHIP_ISTP_ISTB_MASK         0xFFFFFC00u
#define CHIP_ISTP_ISTB_SHIFT        0x0000000Au
#define CHIP_ISTP_ISTB_DEFAULT      0x00000000u

#define CHIP_ISTP_HPEINT_MASK       0x000003E0u
#define CHIP_ISTP_HPEINT_SHIFT      0x00000005u
#define CHIP_ISTP_HPEINT_DEFAULT    0x00000000u

/******************************************************************************\
*              IRP - maskable interrupt return pointer
*
* IRP[31:0] - rw
*
\******************************************************************************/
extern far cregister volatile Uint32 IRP;

#define CHIP_IRP_DEFAULT            0x00000000u

#define CHIP_IRP_IRP_MASK           0xFFFFFFFFu
#define CHIP_IRP_IRP_SHIFT          0x00000000u
#define CHIP_IRP_IRP_DEFAULT        0x00000000u

/******************************************************************************\
*               NRP - non-maskable interrupt return pointer
*
* NRP[31:0] - rw
*