/*******************************************************************************
* COPYRIGHT (C)             中國普天研究院				                       *	
********************************************************************************
* 源文件名: BBU_DD_McbspCsl.h                                                  *
* 功能描述：Registers Description for McBSP in TMS320C6414 and TMS320C6416     *
* 編寫者：louyajun                                                             *
* 版本：1.0.0                                                                  *
* 編制日期：07/20/2004                                                         *
* 說明：                                                                       *
* 修改歷史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* Registers Descriptions for McBSP in TMS320C6414 and TMS320C6416
*-------------------------------------------------------------------------------
*
* DRR0  - serial port 0 data receive register
* DRR1  - serial port 1 data receive register
* DRR2  - serial port 2 data receive register
*
* DXR0  - serial port 0 data transmit register
* DXR1  - serial port 1 data transmit register
* DXR2  - serial port 2 data transmit register
*
* SPCR0 - serial port 0 control register
* SPCR1 - serial port 1 control register
* SPCR2 - serial port 2 control register
*
* RCR0  - serial port 0 receive control register
* RCR1  - serial port 1 receive control register
* RCR2  - serial port 2 receive control register
*
* XCR0  - serial port 0 transmit control register
* XCR1  - serial port 1 transmit control register
* XCR2  - serial port 2 transmit control register
*
* SRGR0 - serial port 0 sample rate generator register
* SRGR1 - serial port 1 sample rate generator register
* SRGR2 - serial port 2 sample rate generator register
*
* MCR0  - serial port 0 multichannel control register
* MCR1  - serial port 1 multichannel control register
* MCR2  - serial port 2 multichannel control register
*
* RCERE00 - serial port 0 Enhanced receive channel enable register 0 
* RCERE01 - serial port 1 Enhanced receive channel enable register 0  
* RCERE02 - serial port 2 Enhanced receive channel enable register 0 
*
* RCERE10 - serial port 0 Enhanced receive channel enable register 1
* RCERE11 - serial port 1 Enhanced receive channel enable register 1 
* RCERE12 - serial port 2 Enhanced receive channel enable register 1
*
* RCERE20 - serial port 0 Enhanced receive channel enable register 2
* RCERE21 - serial port 1 Enhanced receive channel enable register 2 
* RCERE22 - serial port 2 Enhanced receive channel enable register 2
*
* RCERE30 - serial port 0 Enhanced receive channel enable register 3
* RCERE31 - serial port 1 Enhanced receive channel enable register 3 
* RCERE32 - serial port 2 Enhanced receive channel enable register 3
*
* XCERE00 - serial port 0 Enhanced transmit channel enable register 0
* XCERE01 - serial port 1 Enhanced transmit channel enable register 0 
* XCERE02 - serial port 2 Enhanced transmit channel enable register 0
*
* XCERE10 - serial port 0 Enhanced transmit channel enable register 1
* XCERE11 - serial port 1 Enhanced transmit channel enable register 1 
* XCERE12 - serial port 2 Enhanced transmit channel enable register 1
*
* XCERE20 - serial port 0 Enhanced transmit channel enable register 2
* XCERE21 - serial port 1 Enhanced transmit channel enable register 2 
* XCERE22 - serial port 2 Enhanced transmit channel enable register 2
*
* XCERE30 - serial port 0 Enhanced transmit channel enable register 3
* XCERE31 - serial port 1 Enhanced transmit channel enable register 3 
* XCERE32 - serial port 2 Enhanced transmit channel enable register 3
*
* PCR0  - serial port 0 pin control register
* PCR1  - serial port 1 pin control register
* PCR2  - serial port 2 pin control register
*
\******************************************************************************/

#ifndef _BBU_DD_MCBSPCSL_H_
#define _BBU_DD_MCBSPCSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_IrqCsl.h"
#include "BBU_DD_EdmaCsl.h"

/******************************************************************************\
* McBSP Port Base Address Definitions 
\******************************************************************************/
#define MCBSP_PORT_CNT              3
#define MCBSP_BASE_PORT0            0x018C0000u
#define MCBSP_BASE_PORT1            0x01900000u
#define MCBSP_BASE_PORT2            0x01A40000u
/*----------------------------------------------------------------------------*/

/******************************************************************************\
*              McBSP Ports Data Receive Registers Definitions 
*  
* DRR0   - serial port 0 data receive register
* DRR1   - serial port 1 data receive register
* DRR2   - serial port 2 data receive register
*
* DR - r
*
\******************************************************************************/
#define MCBSP_DRR_OFFSET            0
#define MCBSP_DRR0_ADDR             0x30000000u
#define MCBSP_DRR1_ADDR             0x34000000u
#define MCBSP_DRR2_ADDR             0x38000000u
#define MCBSP_DRR_DEFAULT           0x00000000u

#define MCBSP_DRR_DR_MASK           0xFFFFFFFFu
#define MCBSP_DRR_DR_SHIFT          0x00000000u
#define MCBSP_DRR_DR_DEFAULT        0x00000000u

/******************************************************************************\
*              McBSP Ports Data Transmit Registers Definitions 
*  
* DXR0   - serial port 0 data transmit register
* DXR1   - serial port 1 data transmit register
* DXR2   - serial port 2 data transmit register
*
* DX - w
*
\******************************************************************************/
#define MCBSP_DXR_OFFSET            1
#define MCBSP_DXR0_ADDR             0x30000000u
#define MCBSP_DXR1_ADDR             0x34000000u
#define MCBSP_DXR2_ADDR             0x38000000u
#define MCBSP_DXR_DEFAULT           0x00000000u

#define MCBSP_DXR_DX_MASK           0xFFFFFFFFu
#define MCBSP_DXR_DX_SHIFT          0x00000000u
#define MCBSP_DXR_DX_DEFAULT        0x00000000u

/******************************************************************************\
*              McBSP Ports Control Registers Definitions 
*  
* SPCR0  - serial port 0 control register
* SPCR1  - serial port 1 control register
* SPCR2  - serial port 2 control register
*
* FREE[25]       - rw, Free running enable mode bit.This bit is used with SOFT
*                      bit to determine state of serial port clock during
*                      emulation halt              
* SOFT[24]       - rw, Soft bit enable mode bit. This bit is used with FREE
*                      bit to determine state of serial port clock during
*                      emulation halt. This bit has no effect if FREE = 1
* FRST[23]       - rw, Frame-sync generator reset bit
* GRST[22]       - rw, Sample-rate generator reset bit
* XINTM[21:20]   - rw, Transmit interrupt mode bit
* XSYNCERR[19]   - rw, Transmit synchronization error bit. Writing a 1 to
*                      XSYNCERR sets the error condition when the transmitter is
*                      enabled (XRST = 1).It is used mainly for testing purposes
* XEMPTY[18]     - r,  Transmit shift register empty bit
* XRDY[17]       - r,  Transmitter ready bit
* XRST[16]       - rw, Transmitter reset bit resets or enables the transmitter
* DLB[15]        - rw, Digital loop back mode enable bit
* RJUST[14:13]   - rw, Receive sign-extension and justification mode bit
* CLKSTP[12:11]  - rw, Clock stop mode bit. In SPI mode, operates with CLKXP bit
*                      of pin control register (PCR)
* DXENA[7]       - rw, DX enabler enable bit
* RINTM[5:4]     - rw, Receive interrupt mode bit
* RSYNCERR[3]    - rw, Receive synchronization error bit. Writing a 1 to
*                      RSYNCERR sets the error condition when the receiver is
*                      enabled (RRST = 1).It is used mainly for testing purposes
* RFULL[2]       - r,  Receive shift register full bit
* RRDY[1]        - r,  Receiver ready bit
* RRST[0]        - rw, Receiver reset bit resets or enables the receiver
*
\******************************************************************************/
#define MCBSP_SPCR_OFFSET           2
#define MCBSP_SPCR0_ADDR            0x018C0008u
#define MCBSP_SPCR1_ADDR            0x01900008u
#define MCBSP_SPCR2_ADDR            0x01A40008u
#define MCBSP_SPCR_DEFAULT          0x00000000u

#define MCBSP_SPCR_FREE_MASK        0x02000000u
#define MCBSP_SPCR_FREE_SHIFT       0x00000019u
#define MCBSP_SPCR_FREE_DEFAULT     0x00000000u
#define MCBSP_SPCR_FREE_NO          0x00000000u /* Free running mode is disabled
                                                   During emulation halt,SOFT
                                                   bit determines operation of
                                                   McBSP */
#define MCBSP_SPCR_FREE_YES         0x00000001u /* Free running mode is enabled.
                                                   During emulation halt, serial
                                                   clocks continue to run */ 

#define MCBSP_SPCR_SOFT_MASK        0x01000000u
#define MCBSP_SPCR_SOFT_SHIFT       0x00000018u
#define MCBSP_SPCR_SOFT_DEFAULT     0x00000000u
#define MCBSP_SPCR_SOFT_NO          0x00000000u /* Soft mode is disabled. Serial
                                                   port clock stops immediately
                                                   during emulation halt */
#define MCBSP_SPCR_SOFT_YES         0x00000001u /* Soft mode is enabled. serial
                                                   port clock stops after
                                                   completion of current
                                                   transmission during emulation
                                                   halt */ 

#define MCBSP_SPCR_FRST_MASK        0x00800000u
#define MCBSP_SPCR_FRST_SHIFT       0x00000017u
#define MCBSP_SPCR_FRST_DEFAULT     0x00000000u

#define MCBSP_SPCR_FRST_YES         0x00000000u /* Frame sync logic is reset.
                                                   FSG signal is not generated
                                                   by sample-rate generator */
#define MCBSP_SPCR_FRST_NO          0x00000001u /* FSG signal is generated */

#define MCBSP_SPCR_GRST_MASK        0x00400000u
#define MCBSP_SPCR_GRST_SHIFT       0x00000016u
#define MCBSP_SPCR_GRST_DEFAULT     0x00000000u
#define MCBSP_SPCR_GRST_YES         0x00000000u /* Sample rate generator is
                                                   reset*/
#define MCBSP_SPCR_GRST_NO          0x00000001u /* Sample rate generator is
                                                   taken out of reset. CLKG is
                                                   driven as programmed value
                                                   in SRGR register */

#define MCBSP_SPCR_XINTM_MASK       0x00300000u
#define MCBSP_SPCR_XINTM_SHIFT      0x00000014u
#define MCBSP_SPCR_XINTM_DEFAULT    0x00000000u
#define MCBSP_SPCR_XINTM_XRDY       0x00000000u /* XINT is driven by XRDY