?? main.lst
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Sunplus 6502 Assembler - Version 1.6.8
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1 ;==================================================================================
2 ; The information contained herein is the exclusive property of
3 ; Sunplus Technology Co. And shall not be distributed, reproduced,
4 ; or disclosed in whole in part without prior written permission.
5 ; (C) COPYRIGHT 2004 SUNPLUS TECHNOLOGY CO.
6 ; ALL RIGHTS RESERVED
7 ; The entire notice above must be reproduced on all authorized copies.
8 ;==================================================================================
9
10 ;==================================================================================
11 ; Project Name :
12 ; Applied Body : SPMC65P2404A
13 ; Firmware version:
14 ; Programer :
15 ; Date : 2005-1-19
16 ; Description : The Program presents how to scan 16 Keys with the function
17 ; of ADC.
18 ;
19 ; Hardware Connect:
20 ; Link File :
21 ; IDE Version : V1.6.5
22 ; BODY Version : V1.7.0
23 ;==================================================================================
24 .SYNTAX 6502 ;Process standard 6502 addressing syntax
25 .LINKLIST ;Generate linklist information
26 .SYMBOLS ;Generate symbolic debug information
27 ;**********************************************************************************
28 ;* *
29 ;* System Register Define *
30 ;* *
31 ;**********************************************************************************
32 .INCLUDE SPMC65P2404A.inc ;Define all hardware,Registers and ports.
33 < ;; ********************************************************************************
34 < ;; *** Copyright 2000-2008 Sunplus Technology Co., Ltd. All right reserved. ***
35 < ;; *** Header Name : SPMC65P2102A.inc ***
36 < ;; *** Programmer : Darrell Yang ***
37 < ;; *** Data : 2005/04/22 ***
38 < ;; *** Revision : V1.7.0 ***
39 < ;; ********************************************************************************
40 <
41 < ;=======================================================================
42 < ;SPMC65P2404A Input/Output Ports and Data Direction Registers
43 < ;=======================================================================
44 < P_IOA_Data: EQU $00 ; Port A data b0~b7(A)
45 < P_IOB_Data: EQU $01 ; Port B data b0~b5(A)
46 < P_IOC_Data: EQU $02 ; Port C data b0~b3(A)
47 < P_IOD_Data: EQU $03 ; Port D data b0~b2(A)
48 < P_IOA_Dir: EQU $04 ; Port A direction control b0~b7(W), 0=In, 1=Out
49 < P_IOB_Dir: EQU $05 ; Port B direction control b0~b7(W)
50 < P_IOC_Dir: EQU $06 ; Port C direction control b0~b7(W)
51 < P_IOD_Dir: EQU $07 ; Port D direction control b0~b7(W)
52 < P_IOA_Attrib: EQU $08 ; Port A attribute register b0~b7(W)
53 < P_IOB_Attrib: EQU $09 ; Port B attribute register b0~b7(W)
54 < P_IOC_Attrib: EQU $0A ; Port C attribute register b0~b7(W)
55 < P_IOD_Attrib: EQU $0B ; Port D attribute register b0~b7(W)
56 < ;
57 < ;-----------------------------------------------------------------------------------------------------
58 < P_INT_Flag0: EQU $0C ; Interrupt Flag 0.(A)
59 < C_INT_ADIF: EQU %10000000 ; A/D INT flag bit.(A)
60 < C_INT_WDIF: EQU %01000000 ; WDT INT flag bit.(A)
61 < C_INT_IRQ3IF: EQU %00001000 ; IRQ3 INT flag bit.(A)
62 < C_INT_IRQ2IF: EQU %00000100 ; IRQ2 INT flag bit.(A)
63 < C_INT_IRQ1IF: EQU %00000010 ; IRQ1 INT flag bit.(A)
64 < C_INT_IRQ0IF: EQU %00000001 ; IRQ0 INT flag bit.(A)
65 < C_INT_CAP3IF: EQU %00000010 ; CAP3 INT flag bit.(A)
66 < C_INT_CAP2IF: EQU %00000001 ; CAP2 INT flag bit.(A)
67 <
68 < CB_INT_ADIF: EQU 7 ; A/D INT flag bit for bit mode.(A)
69 < CB_INT_WDIF: EQU 6 ; WDT INT flag bit for bit mode.(A)
70 < CB_INT_IRQ3IF: EQU 3 ; IRQ3 INT flag bit for bit mode.(A)
71 < CB_INT_IRQ2IF: EQU 2 ; IRQ2 INT flag bit for bit mode.(A)
72 < CB_INT_IRQ1IF: EQU 1 ; IRQ1 INT flag bit for bit mode.(A)
73 < CB_INT_IRQ0IF: EQU 0 ; IRQ0 INT flag bit for bit mode.(A)
74 < CB_INT_CAP3IF: EQU 1 ; CAP3 INT flag bit for bit mode.(A)
75 < CB_INT_CAP2IF: EQU 0 ; CAP2 INT flag bit for bit mode.(A)
76 < ;
77 < P_INT_Ctrl0: EQU $0D ; Interrupt control 0.(A)
78 < C_INT_ADIE: EQU %10000000 ; A/D INT enable bit.(A)
79 < C_INT_WDIE: EQU %01000000 ; WDT INT enable bit.(A)
80 < C_INT_IRQ3IE: EQU %00001000 ; IRQ3 INT enable bit.(A)
81 < C_INT_IRQ2IE: EQU %00000100 ; IRQ2 INT enable bit.(A)
82 < C_INT_IRQ1IE: EQU %00000010 ; IRQ1 INT enable bit.(A)
83 < C_INT_IRQ0IE: EQU %00000001 ; IRQ0 INT enable bit.(A)
84 < C_INT_CAP3IE: EQU %00000010 ; CAP3 INT enable bit.(A)
85 < C_INT_CAP2IE: EQU %00000001 ; CAP2 INT enable bit.(A)
86 <
87 < CB_INT_ADIE: EQU 7 ; A/D INT enable bit for bit mode.(A)
88 < CB_INT_WDIE: EQU 6 ; WDT INT enable bit for bit mode.(A)
89 < CB_INT_IRQ3IE: EQU 3 ; IRQ3 INT enable bit for bit mode.(A)
90 < CB_INT_IRQ2IE: EQU 2 ; IRQ2 INT enable bit for bit mode.(A)
91 < CB_INT_IRQ1IE: EQU 1 ; IRQ1 INT enable bit for bit mode.(A)
92 < CB_INT_IRQ0IE: EQU 0 ; IRQ0 INT enable bit for bit mode.(A)
93 < CB_INT_CAP3IE: EQU 1 ; CAP3 INT enable bit for bit mode.(A)
94 < CB_INT_CAP2IE: EQU 0 ; CAP2 INT enable bit for bit mode.(A)
95 < ;
96 < P_INT_Flag1: EQU $0E ; Interrupt flag 1.
97 < C_INT_CAP1IF: EQU %10000000 ; CAP1 INT flag bit.(A)
98 < C_INT_CAP0IF: EQU %01000000 ; CAP0 INT flag bit.(A)
99 < C_INT_T3OIF: EQU %00001000 ; Timer3 overflow INT flag bit.(A)
100 < C_INT_T2OIF: EQU %00000100 ; Timer2 overflow INT flag bit.(A)
101 < C_INT_T1OIF: EQU %00000010 ; Timer1 overflow INT flag bit.(A)
102 < C_INT_T0OIF: EQU %00000001 ; Timer0 overflow INT flag bit.(A)
103 <
104 < CB_INT_CAP1IF: EQU 7 ; CAP1 INT flag bit for bit mode.(A)
105 < CB_INT_CAP0IF: EQU 6 ; CAP0 INT flag bit for bit mode.(A)
106 < CB_INT_T3OIF: EQU 3 ; Timer3 overflow INT flag bit for bit mode.(A)
107 < CB_INT_T2OIF: EQU 2 ; Timer2 overflow INT flag bit for bit mode.(A)
108 < CB_INT_T1OIF: EQU 1 ; Timer1 overflow INT flag bit for bit mode.(A)
109 < CB_INT_T0OIF: EQU 0 ; Timer0 overflow INT flag bit for bit mode.(A)
110 < ;
111 < P_INT_Ctrl1: EQU $0F ; Interrupt control 1.
112 < C_INT_CAP1IE: EQU %10000000 ; CAP1 INT enable bit.(A)
113 < C_INT_CAP0IE: EQU %01000000 ; CAP0 INT enable bit.(A)
114 < C_INT_T3OIE: EQU %00001000 ; Timer3 overflow INT enable bit.(A)
115 < C_INT_T2OIE: EQU %00000100 ; Timer2 overflow INT enable bit.(A)
116 < C_INT_T1OIE: EQU %00000010 ; Timer1 overflow INT enable bit.(A)
117 < C_INT_T0OIE: EQU %00000001 ; Timer0 overflow INT enable bit.(A)
118 <
119 < CB_INT_CAP1IE: EQU 7 ; CAP1 INT enable bit for bit mode.(A)
120 < CB_INT_CAP0IE: EQU 6 ; CAP0 INT enable bit for bit mode.(A)
121 < CB_INT_T3OIE: EQU 3 ; Timer3 overflow INT enable bit for bit mode.(A)
122 < CB_INT_T2OIE: EQU 2 ; Timer2 overflow INT enable bit for bit mode.(A)
123 < CB_INT_T1OIE: EQU 1 ; Timer1 overflow INT enable bit for bit mode.(A)
124 < CB_INT_T0OIE: EQU 0 ; Timer0 overflow INT enable bit for bit mode.(A)
125 < ;
126 < P_INT_Flag2: EQU $26 ; Interrupt flag 2.
127 < C_INT_ITVALIF: EQU %00100000 ; Timer Base interrupt flag.
128 < C_INT_SPIIF: EQU %00000100 ; SPI interrupt flag.
129 <
130 < CB_INT_ITVALIF: EQU 5 ; Timer Base interrupt flag for bit mode.
131 < CB_INT_SPIIF: EQU 2 ; SPI interrupt flag for bit mode.
132 < ;
133 < P_INT_Ctrl2: EQU $27 ; Interrupt control 2.
134 < C_INT_ITVALIE: EQU %00100000 ; Timer Base interrupt enable bit.
135 <
136 < CB_INT_ITVALIE: EQU 5 ; Timer Base interrupt enable bit for bit mode.
137 < ;
138 < P_WDT_Clr: EQU $10 ; Watchdog clear register.(W), $55= clear
139 < C_WDT_Clr: EQU $55 ; Write '55' to clear this register.
140 < ;
141 < ;-----------------------------------------------------------------------------------------------------
142 < P_TMR0_1_Ctrl0: EQU $11 ; Timer0/1 control 0.
143 < C_T112B_PWM: EQU %01110000 ; Timer1 Function as 12 Bit PWM.
144 < C_T116B_CAP: EQU %01100000 ; Timer1 Function as 16 Bit Capture(Width).
145 < C_T116B_COMP: EQU %01010000 ; Timer1 Function as 16 Bit Compare.
146 < C_T116B_Timer: EQU %01000000 ; Timer1 Function as 16 Bit Timer.
147 < C_T18B_CAP: EQU %00110000 ; Timer1 Function as 8 Bit Capture(Width,Cycle).
148 < C_T18B_COMP: EQU %00100000 ; Timer1 Function as 8 Bit Compare.
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