?? main.lst
字號:
149 < C_T18B_Timer: EQU %00010000 ; Timer1 Function as 8 Bit Timer.
150 < C_T08B_CAP: EQU %00000011 ; Timer0 Function as 8 Bit Capture(Width).
151 < C_T08B_COMP: EQU %00000010 ; Timer0 Function as 8 Bit Compare.
152 < C_T08B_Timer: EQU %00000001 ; Timer0 Function as 8 Bit Timer.
153 < ;
154 < P_TMR0_1_Ctrl1: EQU $12 ; Timer0/1 control 1.
155 < C_T1EXT_EN: EQU %01110000 ; External Event
156 < C_T1FCS_Div_512: EQU %01100000 ; Timer1 Clock= FCS/512.
157 < C_T1FCS_Div_128: EQU %01010000 ; Timer1 Clock= FCS/128.
158 < C_T1FCS_Div_32: EQU %01000000 ; Timer1 Clock= FCS/32.
159 < C_T1FCS_Div_8: EQU %00110000 ; Timer1 Clock= FCS/8.
160 < C_T1FCS_Div_4: EQU %00100000 ; Timer1 Clock= FCS/4.
161 < C_T1FCS_Div_2: EQU %00010000 ; Timer1 Clock= FCS/2.
162 < C_T1FCS_Div_1: EQU %00000000 ; Timer1 Clock= FCS/1.
163 < C_T0EXT_EN: EQU %00000111 ; External Event
164 < C_T0FCS_Div_512: EQU %00000110 ; Timer0 Clock= FCS/512.
165 < C_T0FCS_Div_128: EQU %00000101 ; Timer0 Clock= FCS/128.
166 < C_T0FCS_Div_32: EQU %00000100 ; Timer0 Clock= FCS/32.
167 < C_T0FCS_Div_8: EQU %00000011 ; Timer0 Clock= FCS/8.
168 < C_T0FCS_Div_4: EQU %00000010 ; Timer0 Clock= FCS/4.
169 < C_T0FCS_Div_2: EQU %00000001 ; Timer0 Clock= FCS/2.
170 < C_T0FCS_Div_1: EQU %00000000 ; Timer0 Clock= FCS/1.
171 < ;
172 < P_TMR0_Count: EQU $13 ; Timer0 8-bit counter register.(R)
173 < P_TMR0_Preload: EQU $13 ; Timer0 8-bit preload register.(W)
174 < P_TMR0_Comp: EQU $13 ; Timer0 8-bit compare low byte value.
175 < P_TMR0_Cap: EQU $13 ; Timer0 8-bit capture low byte width value.
176 < ;
177 < P_TMR1_Count: EQU $15 ; Timer1 8/16-bit Counter register.(R)
178 < P_TMR1_Preload: EQU $15 ; Timer1 8/16-bit preload register.(W)
179 < P_TMR1_Comp: EQU $15 ; Timer1 8/16-bit compare low byte value.
180 < P_TMR1_Cap: EQU $15 ; Timer1 8/16-bit capture low byte width value.
181 < P_TMR1_PWMPeriod: EQU $15 ; Timer1 12-bit PWM peroid low byte register.
182 < ;
183 < P_TMR1_CountHi: EQU $16 ; Timer1 16-bit Counter register.(R)
184 < P_TMR1_PreloadHi: EQU $16 ; Timer1 16-bit preload register.(W)
185 < P_TMR1_CompHi: EQU $16 ; Timer1 16-bit compare high byte value.
186 < P_TMR1_CapHi: EQU $16 ; Timer1 16-bit capture high byte width value.
187 < P_TMR1_CapCycle8: EQU $16 ; Timer1 8-bit capture cycle value.(R)
188 < P_TMR1_DutyPeriod: EQU $16 ; Timer1 12-bit PWM high byte register.
189 < ;
190 < P_TMR1_PWMDuty: EQU $17 ; Timer1 12-bit PWM duty low byte register.
191 < ;
192 < P_TMR2_3_Ctrl0: EQU $18 ; Timer2/3 control 0.
193 < C_T312B_PWM: EQU %01110000 ; Timer3 Function as 12 Bit PWM.
194 < C_T316B_CAP: EQU %01100000 ; Timer3 Function as 16 Bit Capture(Width).
195 < C_T316B_COMP: EQU %01010000 ; Timer3 Function as 16 Bit Compare.
196 < C_T316B_Timer: EQU %01000000 ; Timer3 Function as 16 Bit Timer.
197 < C_T38B_CAP: EQU %00110000 ; Timer3 Function as 8 Bit Capture(Width,Cycle).
198 < C_T38B_COMP: EQU %00100000 ; Timer3 Function as 8 Bit Compare.
199 < C_T38B_Timer: EQU %00010000 ; Timer3 Function as 8 Bit Timer.
200 < C_T28B_CAP: EQU %00000011 ; Timer2 Function as 8 Bit Capture(Width).
201 < C_T28B_COMP: EQU %00000010 ; Timer2 Function as 8 Bit Compare.
202 < C_T28B_Timer: EQU %00000001 ; Timer2 Function as 8 Bit Timer.
203 < ;
204 < P_TMR2_3_Ctrl1: EQU $19 ; Timer3/2 control 1.
205 < C_T3EXT_EN: EQU %01110000 ; External Event
206 < C_T3FCS_Div_512: EQU %01100000 ; Timer3 Clock= FCS/512.
207 < C_T3FCS_Div_128: EQU %01010000 ; Timer3 Clock= FCS/128.
208 < C_T3FCS_Div_32: EQU %01000000 ; Timer3 Clock= FCS/32.
209 < C_T3FCS_Div_8: EQU %00110000 ; Timer3 Clock= FCS/8.
210 < C_T3FCS_Div_4: EQU %00100000 ; Timer3 Clock= FCS/4.
211 < C_T3FCS_Div_2: EQU %00010000 ; Timer3 Clock= FCS/2.
212 < C_T3FCS_Div_1: EQU %00000000 ; Timer3 Clock= FCS/1.
213 < C_T2EXT_EN: EQU %00000111 ; External Event.
214 < C_T2FCS_Div_512: EQU %00000110 ; Timer2 Clock= FCS/512.
215 < C_T2FCS_Div_128: EQU %00000101 ; Timer2 Clock= FCS/128.
216 < C_T2FCS_Div_32: EQU %00000100 ; Timer2 Clock= FCS/32.
217 < C_T2FCS_Div_8: EQU %00000011 ; Timer2 Clock= FCS/8.
218 < C_T2FCS_Div_4: EQU %00000010 ; Timer2 Clock= FCS/4.
219 < C_T2FCS_Div_2: EQU %00000001 ; Timer2 Clock= FCS/2.
220 < C_T2FCS_Div_1: EQU %00000000 ; Timer2 Clock= FCS/1.
221 < ;
222 < P_TMR2_Count: EQU $1A ; Timer2 8-bit counter register.(R)
223 < P_TMR2_Preload: EQU $1A ; Timer2 8-bit preload register.(W)
224 < P_TMR2_Cap: EQU $1A ; Timer2 8-bit capture low byte width value.
225 < ;
226 < P_TMR3_Count: EQU $1C ; Timer3 8/16-bit Counter register.(R)
227 < P_TMR3_Preload: EQU $1C ; Timer3 8/16-bit preload register.(W)
228 < P_TMR3_Comp: EQU $1C ; Timer3 8/16-bit compare low byte value.
229 < P_TMR3_Cap: EQU $1C ; Timer3 8-bit capture low byte width value.
230 < P_TMR3_PWMPeriod: EQU $1C ; Timer3 12-bit PWM peroid low byte register.
231 < ;
232 < P_TMR3_CountHi: EQU $1D ; Timer3 16-bit Counter register.(R)
233 < P_TMR3_PreloadHi: EQU $1D ; Timer3 16-bit preload register.(W)
234 < P_TMR3_CompHi: EQU $1D ; Timer3 16-bit compare high byte value.
235 < P_TMR3_CapHi: EQU $1D ; Timer3 16-bit capture high byte width value.
236 < P_TMR3_CapCycle8: EQU $1D ; Timer3 8-bit capture cycle value.(R)
237 < P_TMR3_DutyPeriod: EQU $1D ; Timer3 12-bit PWM high byte register.
238 < ;
239 < P_TMR3_PWMDuty: EQU $1E ; Timer3 12-bit PWM duty low byte register.
240 < ;
241 < ;-----------------------------------------------------------------------------------------------------
242 < P_AD_Ctrl0: EQU $28 ; A/D converter control 0.
243 < C_AD_EN: EQU %10000000 ; ADC enable control.(A)
244 < C_AD_VRT: EQU %01000000 ; ADC bottom voltage source select bit.(A)
245 < C_AD_CS_2: EQU %00000000 ; 000=Fcpu/2.
246 < C_AD_CS_4: EQU %00000010 ; 001=Fcpu/4.
247 < C_AD_CS_8: EQU %00000100 ; 010=Fcpu/8.
248 < C_AD_CS_16: EQU %00000110 ; 011=Fcpu/16.
249 < C_AD_CS_32: EQU %00001000 ; 100=Fcpu/32.
250 < C_AD_CS_64: EQU %00001010 ; 101=Fcpu/64.
251 < C_AD_CS_128: EQU %00001100 ; 110=Fcpu/128.
252 < C_AD_CS_256: EQU %00001110 ; 111=Fcpu/256.
253 < C_AD_RDY: EQU %00000001 ; ADC status bit.(R)
254 < C_AD_Start: EQU %00000000 ; ADC conversion start bit.(W)
255 <
256 < CB_AD_EN: EQU 7 ; ADC enable control for bit mode.(A)
257 < CB_AD_VRT: EQU 6 ; ADC bottom voltage source select bit for bit mode.(A)
258 < CB_AD_RDY: EQU 0 ; ADC status bit for bit mode.(R)
259 < CB_AD_Start: EQU 0 ; ADC conversion start bit for bit mode.(W)
260 < ;
261 < P_AD_Ctrl1: EQU $29 ; A/D converter control 1.
262 < C_AD_Pin0: EQU %00000001 ; Analog input Port Configuration: channel 0.
263 < C_AD_Pin1: EQU %00000010 ; Analog input Port Configuration: channel 1.
264 < C_AD_Pin2: EQU %00000100 ; Analog input Port Configuration: channel 2.
265 < C_AD_Pin3: EQU %00001000 ; Analog input Port Configuration: channel 3.
266 < C_AD_Pin4: EQU %00010000 ; Analog input Port Configuration: channel 4.
267 < C_AD_Pin5: EQU %00100000 ; Analog input Port Configuration: channel 5.
268 < C_AD_Pin6: EQU %01000000 ; Analog input Port Configuration: channel 6.
269 < C_AD_Pin7: EQU %10000000 ; Analog input Port Configuration: channel 7.
270 <
271 < CB_AD_Pin0: EQU 0 ; Analog input Port Configuration: channel 0 for bit mode.
272 < CB_AD_Pin1: EQU 1 ; Analog input Port Configuration: channel 1 for bit mode.
273 < CB_AD_Pin2: EQU 2 ; Analog input Port Configuration: channel 2 for bit mode.
274 < CB_AD_Pin3: EQU 3 ; Analog input Port Configuration: channel 3 for bit mode.
275 < CB_AD_Pin4: EQU 4 ; Analog input Port Configuration: channel 4 for bit mode.
276 < CB_AD_Pin5: EQU 5 ; Analog input Port Configuration: channel 5 for bit mode.
277 < CB_AD_Pin6: EQU 6 ; Analog input Port Configuration: channel 6 for bit mode.
278 < CB_AD_Pin7: EQU 7 ; Analog input Port Configuration: channel 7 for bit mode.
279 < ;
280 < P_AD_Ctrl2: EQU $2A ; A/D converter control 2.
281 < C_AD_CE: EQU %10000000 ; ADC power control bit.(A)
282 < C_AD_Ch0: EQU %00000000 ; 0000:channel 0.
283 < C_AD_Ch1: EQU %00001000 ; 0001:channel 1.
284 < C_AD_Ch2: EQU %00010000 ; 0010:channel 2.
285 < C_AD_Ch3: EQU %00011000 ; 0011:channel 3.
286 < C_AD_Ch4: EQU %00100000 ; 0100:channel 4.
287 < C_AD_Ch5: EQU %00101000 ; 0101:channel 5.
288 < C_AD_Ch6: EQU %00110000 ; 0110:channel 6.
289 < C_AD_Ch7: EQU %00111000 ; 0111:channel 7.
290 <
291 < CB_AD_CE: EQU 7 ; ADC power control bit for bit mode.(A)
292 < ;
293 < P_AD_DataHi: EQU $2B ; Converted A/D data[9:2] hi.(R)
294 < P_AD_DataLo: EQU $2C ; Converted A/D data[1:0] low.(R)
295 < ;
296 < ;-----------------------------------------------------------------------------------------------------
297 < P_BUZ_Ctrl: EQU $2D ; Buzzer & Timer base Control.
298 < ; Time Base Prescale select bit. (A)
299 < C_TBASE_Dis: EQU %00000000 ; Time Base disable
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