-- ----------------------------------------------------------------- Module: Butterfly0_entity3-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem11/Butterfly0-- Created: 2009-03-24 16:23:25-- Hierarchy Level: 4------ -------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.numeric_std.ALL;ENTITY Butterfly0_entity3 IS  PORT( clk                               :   IN    std_logic;        reset                             :   IN    std_logic;        enb                               :   IN    std_logic;        BM0                               :   IN    std_logic_vector(3 DOWNTO 0);           BM1                               :   IN    std_logic_vector(3 DOWNTO 0);           SM0                               :   IN    std_logic_vector(3 DOWNTO 0);           SM1                               :   IN    std_logic_vector(3 DOWNTO 0);           DEC0                              :   OUT   std_logic;        DEC1                              :   OUT   std_logic;        NSM0                              :   OUT   std_logic_vector(3 DOWNTO 0);           NSM1                              :   OUT   std_logic_vector(3 DOWNTO 0)           );END Butterfly0_entity3;ARCHITECTURE rtl OF Butterfly0_entity3 IS  -- Component Declarations  COMPONENT ACS0_entity6    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          BM0                             :   IN    std_logic_vector(3 DOWNTO 0);             SM0                             :   IN    std_logic_vector(3 DOWNTO 0);             BM1                             :   IN    std_logic_vector(3 DOWNTO 0);             SM1                             :   IN    std_logic_vector(3 DOWNTO 0);             SM                              :   OUT   std_logic_vector(3 DOWNTO 0);             DEC                             :   OUT   std_logic          );  END COMPONENT;  COMPONENT ACS1_entity6    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          BM0                             :   IN    std_logic_vector(3 DOWNTO 0);             SM0                             :   IN    std_logic_vector(3 DOWNTO 0);             BM1                             :   IN    std_logic_vector(3 DOWNTO 0);             SM1                             :   IN    std_logic_vector(3 DOWNTO 0);             SM                              :   OUT   std_logic_vector(3 DOWNTO 0);             DEC                             :   OUT   std_logic          );  END COMPONENT;  -- Component Configuration Statements  FOR ALL : ACS0_entity6    USE ENTITY work.ACS0_entity6(rtl);  FOR ALL : ACS1_entity6    USE ENTITY work.ACS1_entity6(rtl);  -- Signals  SIGNAL ACS0_out1                        : std_logic_vector(3 DOWNTO 0);     SIGNAL ACS0_out2                        : std_logic;  SIGNAL ACS1_out1                        : std_logic_vector(3 DOWNTO 0);     SIGNAL ACS1_out2                        : std_logic;BEGIN  u_ACS0 : ACS0_entity6    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       BM0 => BM0,          SM0 => SM0,          BM1 => BM1,          SM1 => SM1,          SM => ACS0_out1,          DEC => ACS0_out2       );  u_ACS1 : ACS1_entity6    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       BM0 => BM1,          SM0 => SM0,          BM1 => BM0,          SM1 => SM1,          SM => ACS1_out1,          DEC => ACS1_out2       );  DEC0 <= ACS0_out2;  DEC1 <= ACS1_out2;  NSM0 <= ACS0_out1;  NSM1 <= ACS1_out1;END rtl;