-- ----------------------------------------------------------------- Module: ACS1_entity19-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem3/Butterfly1/ACS1-- Created: 2009-03-24 16:23:32-- Hierarchy Level: 5------ -------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.numeric_std.ALL;use IEEE.std_logic_unsigned.all;ENTITY ACS1_entity19 IS  PORT( clk                               :   IN    std_logic;        reset                             :   IN    std_logic;        enb                               :   IN    std_logic;        BM0                               :   IN    std_logic_vector(3 DOWNTO 0);           SM0                               :   IN    std_logic_vector(3 DOWNTO 0);           BM1                               :   IN    std_logic_vector(3 DOWNTO 0);           SM1                               :   IN    std_logic_vector(3 DOWNTO 0);           SM                                :   OUT   std_logic_vector(3 DOWNTO 0);           DEC                               :   OUT   std_logic        );END ACS1_entity19;ARCHITECTURE rtl OF ACS1_entity19 IS  -- Signals  SIGNAL s                                : std_logic_vector(3 DOWNTO 0);     SIGNAL s_1                              : std_logic_vector(3 DOWNTO 0);     SIGNAL Sum_of_Elements1_out1            : std_logic_vector(3 DOWNTO 0);     SIGNAL s_2                              : std_logic_vector(3 DOWNTO 0);     SIGNAL s_3                              : std_logic_vector(3 DOWNTO 0);     SIGNAL Sum_of_Elements_out1             : std_logic_vector(3 DOWNTO 0);     SIGNAL Relational_Operator1_out1        : std_logic;  SIGNAL Switch_out1                      : std_logic_vector(3 DOWNTO 0);     SIGNAL Logical_Operator_out1            : std_logic;  SIGNAL add_cast                         : std_logic_vector(3 DOWNTO 0);     SIGNAL add_cast_1                       : std_logic_vector(3 DOWNTO 0);     SIGNAL add_cast_2                       : std_logic_vector(3 DOWNTO 0);     SIGNAL add_cast_3                       : std_logic_vector(3 DOWNTO 0);   BEGIN  s <= BM0;  s_1 <= SM0;  add_cast <= s;  add_cast_1 <= s_1;  Sum_of_Elements1_out1 <= add_cast + add_cast_1;    s_2 <= BM1;  s_3 <= SM1;  add_cast_2 <= s_2;  add_cast_3 <= s_3;  Sum_of_Elements_out1 <= add_cast_2 + add_cast_3;    Relational_Operator1_out1 <= '1' WHEN ( Sum_of_Elements1_out1 <= Sum_of_Elements_out1 ) ELSE '0';  Switch_out1 <= Sum_of_Elements1_out1 WHEN ( Relational_Operator1_out1 = '1' ) ELSE                 Sum_of_Elements_out1;  SM <= std_logic_vector(Switch_out1);  Logical_Operator_out1 <= NOT(Relational_Operator1_out1);  DEC <= Logical_Operator_out1;END rtl;