-- ----------------------------------------------------------------- Module: viterbi_block-- Simulink Path: hdlcoderviterbi/viterbi_block-- Created: 2009-03-24 16:24:10-- Hierarchy Level: 0--In1  [171 133]--out1 wait for 33 clk and out at the 34 clk'event-- -------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.numeric_std.ALL;USE work.viterbi_block_pkg.ALL;ENTITY viterbi_block IS  PORT( clk                               :   IN    std_logic;        reset                             :   IN    std_logic;        clk_enable                        :   IN    std_logic;        In1                               :   IN    vector_of_std_logic_vector2(0 TO 1);  --[171 133]        ce_out                            :   OUT   std_logic;        Out1                              :   OUT   std_logic        );END viterbi_block;ARCHITECTURE rtl OF viterbi_block IS  -- Component Declarations  COMPONENT BMC_Unit    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          In1                             :   IN    vector_of_std_logic_vector2(0 TO 1);            Out1                            :   OUT   vector_of_std_logic_vector4(0 TO 3)            );  END COMPONENT;  COMPONENT ACS_Unit    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          In1                             :   IN    vector_of_std_logic_vector4(0 TO 3);            Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)            );  END COMPONENT;  COMPONENT Traceback    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]          In2                             :   IN    std_logic_vector(7 DOWNTO 0);            Out1                            :   OUT   std_logic          );  END COMPONENT;  -- Component Configuration Statements  FOR ALL : BMC_Unit    USE ENTITY work.BMC_Unit(rtl);  FOR ALL : ACS_Unit    USE ENTITY work.ACS_Unit(rtl);  FOR ALL : Traceback    USE ENTITY work.Traceback(rtl);  -- Signals  SIGNAL enb                              : std_logic;  SIGNAL BMC_Unit_out1                    : vector_of_std_logic_vector4(0 TO 3);    SIGNAL ACS_Unit_out1                    : std_logic_vector(0 TO 63);  -- boolean [64]  SIGNAL ACS_Unit_acs_out2                : std_logic_vector(7 DOWNTO 0);    SIGNAL Traceback_out1                   : std_logic;  BEGIN  u_BMC_Unit : BMC_Unit    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       In1 => In1,         Out1 => BMC_Unit_out1         );  u_ACS_Unit : ACS_Unit    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       In1 => BMC_Unit_out1,         Out1 => ACS_Unit_out1,  -- boolean [64]       Out2 => ACS_Unit_acs_out2         );  u_Traceback : Traceback    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       In1 => ACS_Unit_out1,  -- boolean [64]       In2 => ACS_Unit_acs_out2,         Out1 => Traceback_out1       );  enb <= clk_enable;  ce_out <= enb;  Out1 <= Traceback_out1;END rtl;