?? subsystem25.vhd
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-- ----------------------------------------------------------------- Module: Subsystem25-- Simulink Path: hdlcoderviterbi/viterbi_block/Traceback/Subsystem25-- Created: 2009-03-24 16:24:03-- Hierarchy Level: 2------ -------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.numeric_std.ALL;ENTITY Subsystem25 IS PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; In1 : IN std_logic_vector(0 TO 63); -- boolean [64] In2 : IN std_logic_vector(7 DOWNTO 0); Out1 : OUT std_logic_vector(0 TO 63); -- boolean [64] Out2 : OUT std_logic_vector(7 DOWNTO 0) );END Subsystem25;ARCHITECTURE rtl OF Subsystem25 IS -- Constants CONSTANT Bitwise_AND_with_Mask_const : unsigned(7 DOWNTO 0) := to_unsigned(62, 8); -- uint8 -- Signals SIGNAL Unit_Delay_out1 : std_logic_vector(0 TO 63); -- boolean [64] SIGNAL s : unsigned(7 DOWNTO 0); -- uint8 SIGNAL Variable_Selector_out1 : std_logic; SIGNAL Data_Type_Conversion_out1 : unsigned(7 DOWNTO 0); -- uint8 SIGNAL Shift_Arithmetic_out1 : unsigned(7 DOWNTO 0); -- uint8 SIGNAL Bitwise_AND_with_Mask_out1 : unsigned(7 DOWNTO 0); -- uint8 SIGNAL Bitwise_Operator_out1 : unsigned(7 DOWNTO 0); -- uint8BEGIN Unit_Delay_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Unit_Delay_out1 <= (OTHERS => '0'); ELSIF clk'event AND clk = '1' THEN IF enb = '1' THEN Unit_Delay_out1(0 TO 63) <= In1(0 TO 63); END IF; END IF; END PROCESS Unit_Delay_process; Out1 <= Unit_Delay_out1; s <= unsigned(In2); Variable_Selector_out1 <= In1(0) WHEN ( s=to_unsigned(0, 8) ) ELSE In1(1) WHEN ( s=to_unsigned(1, 8) ) ELSE In1(2) WHEN ( s=to_unsigned(2, 8) ) ELSE In1(3) WHEN ( s=to_unsigned(3, 8) ) ELSE In1(4) WHEN ( s=to_unsigned(4, 8) ) ELSE In1(5) WHEN ( s=to_unsigned(5, 8) ) ELSE In1(6) WHEN ( s=to_unsigned(6, 8) ) ELSE In1(7) WHEN ( s=to_unsigned(7, 8) ) ELSE In1(8) WHEN ( s=to_unsigned(8, 8) ) ELSE In1(9) WHEN ( s=to_unsigned(9, 8) ) ELSE In1(10) WHEN ( s=to_unsigned(10, 8) ) ELSE In1(11) WHEN ( s=to_unsigned(11, 8) ) ELSE In1(12) WHEN ( s=to_unsigned(12, 8) ) ELSE In1(13) WHEN ( s=to_unsigned(13, 8) ) ELSE In1(14) WHEN ( s=to_unsigned(14, 8) ) ELSE In1(15) WHEN ( s=to_unsigned(15, 8) ) ELSE In1(16) WHEN ( s=to_unsigned(16, 8) ) ELSE In1(17) WHEN ( s=to_unsigned(17, 8) ) ELSE In1(18) WHEN ( s=to_unsigned(18, 8) ) ELSE In1(19) WHEN ( s=to_unsigned(19, 8) ) ELSE In1(20) WHEN ( s=to_unsigned(20, 8) ) ELSE In1(21) WHEN ( s=to_unsigned(21, 8) ) ELSE In1(22) WHEN ( s=to_unsigned(22, 8) ) ELSE In1(23) WHEN ( s=to_unsigned(23, 8) ) ELSE In1(24) WHEN ( s=to_unsigned(24, 8) ) ELSE In1(25) WHEN ( s=to_unsigned(25, 8) ) ELSE In1(26) WHEN ( s=to_unsigned(26, 8) ) ELSE In1(27) WHEN ( s=to_unsigned(27, 8) ) ELSE In1(28) WHEN ( s=to_unsigned(28, 8) ) ELSE In1(29) WHEN ( s=to_unsigned(29, 8) ) ELSE In1(30) WHEN ( s=to_unsigned(30, 8) ) ELSE In1(31) WHEN ( s=to_unsigned(31, 8) ) ELSE In1(32) WHEN ( s=to_unsigned(32, 8) ) ELSE In1(33) WHEN ( s=to_unsigned(33, 8) ) ELSE In1(34) WHEN ( s=to_unsigned(34, 8) ) ELSE In1(35) WHEN ( s=to_unsigned(35, 8) ) ELSE In1(36) WHEN ( s=to_unsigned(36, 8) ) ELSE In1(37) WHEN ( s=to_unsigned(37, 8) ) ELSE In1(38) WHEN ( s=to_unsigned(38, 8) ) ELSE In1(39) WHEN ( s=to_unsigned(39, 8) ) ELSE In1(40) WHEN ( s=to_unsigned(40, 8) ) ELSE In1(41) WHEN ( s=to_unsigned(41, 8) ) ELSE In1(42) WHEN ( s=to_unsigned(42, 8) ) ELSE In1(43) WHEN ( s=to_unsigned(43, 8) ) ELSE In1(44) WHEN ( s=to_unsigned(44, 8) ) ELSE In1(45) WHEN ( s=to_unsigned(45, 8) ) ELSE In1(46) WHEN ( s=to_unsigned(46, 8) ) ELSE In1(47) WHEN ( s=to_unsigned(47, 8) ) ELSE In1(48) WHEN ( s=to_unsigned(48, 8) ) ELSE In1(49) WHEN ( s=to_unsigned(49, 8) ) ELSE In1(50) WHEN ( s=to_unsigned(50, 8) ) ELSE In1(51) WHEN ( s=to_unsigned(51, 8) ) ELSE In1(52) WHEN ( s=to_unsigned(52, 8) ) ELSE In1(53) WHEN ( s=to_unsigned(53, 8) ) ELSE In1(54) WHEN ( s=to_unsigned(54, 8) ) ELSE In1(55) WHEN ( s=to_unsigned(55, 8) ) ELSE In1(56) WHEN ( s=to_unsigned(56, 8) ) ELSE In1(57) WHEN ( s=to_unsigned(57, 8) ) ELSE In1(58) WHEN ( s=to_unsigned(58, 8) ) ELSE In1(59) WHEN ( s=to_unsigned(59, 8) ) ELSE In1(60) WHEN ( s=to_unsigned(60, 8) ) ELSE In1(61) WHEN ( s=to_unsigned(61, 8) ) ELSE In1(62) WHEN ( s=to_unsigned(62, 8) ) ELSE In1(63); Data_Type_Conversion_out1 <= resize("0" & Variable_Selector_out1, 8); Shift_Arithmetic_out1 <= resize(s(6 DOWNTO 0) & '0', 8); Bitwise_AND_with_Mask_out1 <= Shift_Arithmetic_out1 AND Bitwise_AND_with_Mask_const; Bitwise_Operator_out1 <= Data_Type_Conversion_out1 OR Bitwise_AND_with_Mask_out1; Out2 <= std_logic_vector(Bitwise_Operator_out1);END rtl;
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