-- ----------------------------------------------------------------- Module: Subsystem9-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem9-- Created: 2009-03-24 16:23:39-- Hierarchy Level: 3------ -------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.numeric_std.ALL;USE work.viterbi_block_pkg.ALL;ENTITY Subsystem9 IS  PORT( clk                               :   IN    std_logic;        reset                             :   IN    std_logic;        enb                               :   IN    std_logic;        SM                                :   IN    vector_of_std_logic_vector4(0 TO 3);          BM                                :   IN    vector_of_std_logic_vector4(0 TO 3);          NSM                               :   OUT   vector_of_std_logic_vector4(0 TO 3);          DEC                               :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]        );END Subsystem9;ARCHITECTURE rtl OF Subsystem9 IS  -- Component Declarations  COMPONENT Butterfly0_entity15    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          BM0                             :   IN    std_logic_vector(3 DOWNTO 0);            BM1                             :   IN    std_logic_vector(3 DOWNTO 0);            SM0                             :   IN    std_logic_vector(3 DOWNTO 0);            SM1                             :   IN    std_logic_vector(3 DOWNTO 0);            DEC0                            :   OUT   std_logic;          DEC1                            :   OUT   std_logic;          NSM0                            :   OUT   std_logic_vector(3 DOWNTO 0);            NSM1                            :   OUT   std_logic_vector(3 DOWNTO 0)            );  END COMPONENT;  COMPONENT Butterfly1_entity15    PORT( clk                             :   IN    std_logic;          reset                           :   IN    std_logic;          enb                             :   IN    std_logic;          BM0                             :   IN    std_logic_vector(3 DOWNTO 0);            BM1                             :   IN    std_logic_vector(3 DOWNTO 0);            SM0                             :   IN    std_logic_vector(3 DOWNTO 0);            SM1                             :   IN    std_logic_vector(3 DOWNTO 0);            DEC0                            :   OUT   std_logic;          DEC1                            :   OUT   std_logic;          NSM0                            :   OUT   std_logic_vector(3 DOWNTO 0);            NSM1                            :   OUT   std_logic_vector(3 DOWNTO 0)            );  END COMPONENT;  -- Component Configuration Statements  FOR ALL : Butterfly0_entity15    USE ENTITY work.Butterfly0_entity15(rtl);  FOR ALL : Butterfly1_entity15    USE ENTITY work.Butterfly1_entity15(rtl);  -- Local Type Definitions  TYPE vector_of_unsigned4 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(3 DOWNTO 0);  -- Signals  SIGNAL s                                : vector_of_unsigned4(0 TO 3);    SIGNAL Demux1_out1                      : std_logic_vector(3 DOWNTO 0);    SIGNAL Demux1_out2                      : std_logic_vector(3 DOWNTO 0);    SIGNAL Demux1_out3                      : std_logic_vector(3 DOWNTO 0);    SIGNAL Demux1_out4                      : std_logic_vector(3 DOWNTO 0);    SIGNAL s_1                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_2                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_3                              : vector_of_unsigned4(0 TO 3);    SIGNAL Demux3_out1                      : std_logic_vector(3 DOWNTO 0);    SIGNAL Demux3_out2                      : std_logic_vector(3 DOWNTO 0);    SIGNAL Demux3_out3                      : std_logic_vector(3 DOWNTO 0);    SIGNAL Demux3_out4                      : std_logic_vector(3 DOWNTO 0);    SIGNAL s_4                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_5                              : std_logic_vector(3 DOWNTO 0);    SIGNAL Butterfly0_out1                  : std_logic;  SIGNAL Butterfly0_out2                  : std_logic;  SIGNAL Butterfly0_out3                  : std_logic_vector(3 DOWNTO 0);    SIGNAL Butterfly0_out4                  : std_logic_vector(3 DOWNTO 0);    SIGNAL s_6                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_7                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_8                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_9                              : std_logic_vector(3 DOWNTO 0);    SIGNAL s_10                             : std_logic_vector(3 DOWNTO 0);    SIGNAL s_11                             : std_logic_vector(3 DOWNTO 0);    SIGNAL Butterfly1_out1                  : std_logic;  SIGNAL Butterfly1_out2                  : std_logic;  SIGNAL Butterfly1_out3                  : std_logic_vector(3 DOWNTO 0);    SIGNAL Butterfly1_out4                  : std_logic_vector(3 DOWNTO 0);    SIGNAL s_12                             : std_logic_vector(3 DOWNTO 0);    SIGNAL s_13                             : std_logic_vector(3 DOWNTO 0);    SIGNAL Mux1_out1                        : vector_of_unsigned4(0 TO 3);    SIGNAL Mux2_out1                        : std_logic_vector(0 TO 3);  -- boolean [4]BEGIN  u_Butterfly0 : Butterfly0_entity15    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       BM0 => s_1,         BM1 => s_2,         SM0 => s_4,         SM1 => s_5,         DEC0 => Butterfly0_out1,       DEC1 => Butterfly0_out2,       NSM0 => Butterfly0_out3,         NSM1 => Butterfly0_out4         );  u_Butterfly1 : Butterfly1_entity15    PORT MAP      (clk => clk,       reset => reset,       enb => enb,       BM0 => s_8,         BM1 => s_9,         SM0 => s_10,         SM1 => s_11,         DEC0 => Butterfly1_out1,       DEC1 => Butterfly1_out2,       NSM0 => Butterfly1_out3,         NSM1 => Butterfly1_out4         );  outputgen2: FOR k IN 0 TO 3 GENERATE    s(k) <= BM(k);  END GENERATE;  Demux1_out1 <= s(0);  Demux1_out2 <= s(1);  Demux1_out3 <= s(2);  Demux1_out4 <= s(3);  s_1 <= std_logic_vector(Demux1_out3);  s_2 <= std_logic_vector(Demux1_out2);  outputgen1: FOR k IN 0 TO 3 GENERATE    s_3(k) <= SM(k);  END GENERATE;  Demux3_out1 <= s_3(0);  Demux3_out2 <= s_3(1);  Demux3_out3 <= s_3(2);  Demux3_out4 <= s_3(3);  s_4 <= std_logic_vector(Demux3_out1);  s_5 <= std_logic_vector(Demux3_out2);  s_6 <= Butterfly0_out3;  s_7 <= Butterfly0_out4;  s_8 <= std_logic_vector(Demux1_out4);  s_9 <= std_logic_vector(Demux1_out1);  s_10 <= std_logic_vector(Demux3_out3);  s_11 <= std_logic_vector(Demux3_out4);  s_12 <= Butterfly1_out3;  s_13 <= Butterfly1_out4;  Mux1_out1(0) <= s_6;  Mux1_out1(1) <= s_7;  Mux1_out1(2) <= s_12;  Mux1_out1(3) <= s_13;  outputgen: FOR k IN 0 TO 3 GENERATE    NSM(k) <= std_logic_vector(Mux1_out1(k));  END GENERATE;  Mux2_out1(0) <= Butterfly0_out1;  Mux2_out1(1) <= Butterfly0_out2;  Mux2_out1(2) <= Butterfly1_out1;  Mux2_out1(3) <= Butterfly1_out2;  DEC <= Mux2_out1;END rtl;