/* linux/include/asm/arch-s3c2410/regs-adc.h*/#ifndef __ASM_ARCH_REGS_ADC_H#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"#define S3C2410_ADCREG(x) (x)#define S3C2410_ADCCON	   S3C2410_ADCREG(0x00)#define S3C2410_ADCTSC	   S3C2410_ADCREG(0x04)#define S3C2410_ADCDLY	   S3C2410_ADCREG(0x08)#define S3C2410_ADCDAT0	   S3C2410_ADCREG(0x0C)#define S3C2410_ADCDAT1	   S3C2410_ADCREG(0x10)/***************************add by lfc***************************/#define S3C2410_ADC_IN0                 0#define S3C2410_ADC_IN1                 1#define S3C2410_ADC_IN2                 2#define S3C2410_ADC_IN3                 3#define S3C2410_ADC_IN4                 4#define S3C2410_ADC_IN5                 5#define S3C2410_ADC_IN6                 6#define S3C2410_ADC_IN7                 7#define S3C2410_ADC_BUSY                1#define S3C2410_ADC_READY               0#define S3C2410_NOP_MODE                0#define S3C2410_X_AXIS_MODE             1#define S3C2410_Y_AXIS_MODE             2#define S3C2410_WAIT_INT_MODE           3/*****************************end add****************************//* ADCCON Register Bits */#define S3C2410_ADCCON_ECFLG		(1<<15)#define S3C2410_ADCCON_PRSCEN   	(1<<14)#define S3C2410_ADCCON_PRSCVL(x)	(((x)&0xFF)<<6)#define S3C2410_ADCCON_PRSCVLMASK	(0xFF<<6)#define S3C2410_ADCCON_SELMUX(x)	(((x)&0x7)<<3)#define S3C2410_ADCCON_MUXMASK		(0x7<<3)#define S3C2410_ADCCON_STDBM		(1<<2)#define S3C2410_ADCCON_READ_START	(1<<1)#define S3C2410_ADCCON_ENABLE_START	(1<<0)#define S3C2410_ADCCON_STARTMASK	(0x3<<0)/**************************add by lfc***********************/#define S3C2410_ADCCON_PRSCDIS          (S3C2410_ADCCON_PRSCEN*0)/***************************end add*************************//* ADCTSC Register Bits *//**************************add by lfc************************/#define S3C2410_UD_SEN                  (1<<8)/***************************end add**************************/#define S3C2410_ADCTSC_YM_SEN		(1<<7)#define S3C2410_ADCTSC_YP_SEN		(1<<6)#define S3C2410_ADCTSC_XM_SEN		(1<<5)#define S3C2410_ADCTSC_XP_SEN		(1<<4)#define S3C2410_ADCTSC_XP_PULL_UP_DIS	(1<<3)#define S3C2410_ADCTSC_AUTO_PST		(1<<2)//#define S3C2410_ADCTSC_XY_PST		(0x3<<0)/**********************modify by lfc**************************/#define S3C2410_ADCTSC_XY_PST(x)        (((x)&0x3)<<0)#define S3C2410_DOWN_INT                (S3C2410_UD_SEN*0)#define S3C2410_UP_INT                  (S3C2410_UD_SEN*1)#define S3C2410_ADCTSC_XM_HIZ           (S3C2410_ADCTSC_XM_SEN*0)#define S3C2410_ADCTSC_XM_GND           (S3C2410_ADCTSC_XM_SEN*1)#define S3C2410_ADCTSC_XP_EXTVLT        (S3C2410_ADCTSC_XP_SEN*0)#define S3C2410_ADCTSC_XP_AIN           (S3C2410_ADCTSC_XP_SEN*1)#define S3C2410_ADCTSC_YM_HIZ           (S3C2410_ADCTSC_YM_SEN*0)#define S3C2410_ADCTSC_YM_GND           (S3C2410_ADCTSC_YM_SEN*1)#define S3C2410_ADCTSC_YP_EXTVLT        (S3C2410_ADCTSC_YP_SEN*0)#define S3C2410_ADCTSC_YP_AIN           (S3C2410_ADCTSC_YP_SEN*1)#define S3C2410_ADCTSC_XP_PULL_UP_EN   (S3C2410_ADCTSC_XP_PULL_UP_DIS*0)/************************end modify***************************//* ADCDAT0 Bits */#define S3C2410_ADCDAT0_UPDOWN		(1<<15)#define S3C2410_ADCDAT0_AUTO_PST	(1<<14)#define S3C2410_ADCDAT0_XY_PST		(0x3<<12)#define S3C2410_ADCDAT0_XPDATA_MASK	(0x03FF)/* ADCDAT1 Bits */#define S3C2410_ADCDAT1_UPDOWN		(1<<15)#define S3C2410_ADCDAT1_AUTO_PST	(1<<14)#define S3C2410_ADCDAT1_XY_PST		(0x3<<12)#define S3C2410_ADCDAT1_YPDATA_MASK	(0x03FF)#endif /* __ASM_ARCH_REGS_ADC_H */