#define _H3800_ASIC2_SPI_Base                  0x0400#define _H3800_ASIC2_SPI_Control               0x0000    /* R/W 8 bits */#define _H3800_ASIC2_SPI_Data                  0x0004    /* R/W 8 bits */#define _H3800_ASIC2_SPI_ChipSelectDisabled    0x0008    /* W   8 bits */#define H3800_ASIC2_SPI_Control             H3800_ASIC2_OFFSET( __u8, SPI, Control )#define H3800_ASIC2_SPI_Data                H3800_ASIC2_OFFSET( __u8, SPI, Data )#define H3800_ASIC2_SPI_ChipSelectDisabled  H3800_ASIC2_OFFSET( __u8, SPI, ChipSelectDisabled )#define _H3800_ASIC2_PWM_0_Base                0x0600#define _H3800_ASIC2_PWM_1_Base                0x0700#define _H3800_ASIC2_PWM_TimeBase              0x0000    /* R/W 6 bits */#define _H3800_ASIC2_PWM_PeriodTime            0x0004    /* R/W 12 bits */#define _H3800_ASIC2_PWM_DutyTime              0x0008    /* R/W 12 bits */#define H3800_ASIC2_PWM_0_TimeBase          H3800_ASIC2_NOFFSET(  __u8, PWM, 0, TimeBase )#define H3800_ASIC2_PWM_0_PeriodTime        H3800_ASIC2_NOFFSET( __u16, PWM, 0, PeriodTime )#define H3800_ASIC2_PWM_0_DutyTime          H3800_ASIC2_NOFFSET( __u16, PWM, 0, DutyTime )#define H3800_ASIC2_PWM_1_TimeBase          H3800_ASIC2_NOFFSET(  __u8, PWM, 1, TimeBase )#define H3800_ASIC2_PWM_1_PeriodTime        H3800_ASIC2_NOFFSET( __u16, PWM, 1, PeriodTime )#define H3800_ASIC2_PWM_1_DutyTime          H3800_ASIC2_NOFFSET( __u16, PWM, 1, DutyTime )#define H3800_ASIC2_PWM_TIMEBASE_MASK             0xf    /* Low 4 bits sets time base, max = 8 */#define H3800_ASIC2_PWM_TIMEBASE_ENABLE    ( 1 << 4 )    /* Enable clock */#define H3800_ASIC2_PWM_TIMEBASE_CLEAR     ( 1 << 5 )    /* Clear the PWM */#define _H3800_ASIC2_LED_0_Base                0x0800#define _H3800_ASIC2_LED_1_Base                0x0880#define _H3800_ASIC2_LED_2_Base                0x0900#define _H3800_ASIC2_LED_TimeBase              0x0000    /* R/W  7 bits */#define _H3800_ASIC2_LED_PeriodTime            0x0004    /* R/W 12 bits */#define _H3800_ASIC2_LED_DutyTime              0x0008    /* R/W 12 bits */#define _H3800_ASIC2_LED_AutoStopCount         0x000c    /* R/W 16 bits */#define H3800_ASIC2_LED_0_TimeBase          H3800_ASIC2_NOFFSET(  __u8, LED, 0, TimeBase )#define H3800_ASIC2_LED_0_PeriodTime        H3800_ASIC2_NOFFSET( __u16, LED, 0, PeriodTime )#define H3800_ASIC2_LED_0_DutyTime          H3800_ASIC2_NOFFSET( __u16, LED, 0, DutyTime )#define H3800_ASIC2_LED_0_AutoStopClock     H3800_ASIC2_NOFFSET( __u16, LED, 0, AutoStopClock )#define H3800_ASIC2_LED_1_TimeBase          H3800_ASIC2_NOFFSET(  __u8, LED, 1, TimeBase )#define H3800_ASIC2_LED_1_PeriodTime        H3800_ASIC2_NOFFSET( __u16, LED, 1, PeriodTime )#define H3800_ASIC2_LED_1_DutyTime          H3800_ASIC2_NOFFSET( __u16, LED, 1, DutyTime )#define H3800_ASIC2_LED_1_AutoStopClock     H3800_ASIC2_NOFFSET( __u16, LED, 1, AutoStopClock )#define H3800_ASIC2_LED_2_TimeBase          H3800_ASIC2_NOFFSET(  __u8, LED, 2, TimeBase )#define H3800_ASIC2_LED_2_PeriodTime        H3800_ASIC2_NOFFSET( __u16, LED, 2, PeriodTime )#define H3800_ASIC2_LED_2_DutyTime          H3800_ASIC2_NOFFSET( __u16, LED, 2, DutyTime )#define H3800_ASIC2_LED_2_AutoStopClock     H3800_ASIC2_NOFFSET( __u16, LED, 2, AutoStopClock )#define H3800_ASIC2_LED_TIMEBASE_MASK            0x0f    /* Low 4 bits sets time base, max = 13 */#define H3800_ASIC2_LED_TIMEBASE_BLINK     ( 1 << 4 )    /* Enable blinking */#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP  ( 1 << 5 )#define H3800_ASIC2_LED_TIMEBASE_ALWAYS    ( 1 << 6 )    /* Enable blink always */#define _H3800_ASIC2_UART_0_Base               0x0A00#define _H3800_ASIC2_UART_1_Base               0x0C00#define _H3800_ASIC2_UART_Receive              0x0000    /* R    8 bits */#define _H3800_ASIC2_UART_Transmit             0x0000    /*   W  8 bits */#define _H3800_ASIC2_UART_IntEnable            0x0004    /* R/W  8 bits */#define _H3800_ASIC2_UART_IntVerify            0x0008    /* R/W  8 bits */#define _H3800_ASIC2_UART_FIFOControl          0x000c    /* R/W  8 bits */#define _H3800_ASIC2_UART_LineControl          0x0010    /* R/W  8 bits */#define _H3800_ASIC2_UART_ModemStatus          0x0014    /* R/W  8 bits */#define _H3800_ASIC2_UART_LineStatus           0x0018    /* R/W  8 bits */#define _H3800_ASIC2_UART_ScratchPad           0x001c    /* R/W  8 bits */#define _H3800_ASIC2_UART_DivisorLatchL        0x0020    /* R/W  8 bits */#define _H3800_ASIC2_UART_DivisorLatchH        0x0024    /* R/W  8 bits */#define H3800_ASIC2_UART_0_Receive          H3800_ASIC2_NOFFSET(  __u8, UART, 0, Receive )#define H3800_ASIC2_UART_0_Transmit         H3800_ASIC2_NOFFSET(  __u8, UART, 0, Transmit )#define H3800_ASIC2_UART_0_IntEnable        H3800_ASIC2_NOFFSET(  __u8, UART, 0, IntEnable )#define H3800_ASIC2_UART_0_IntVerify        H3800_ASIC2_NOFFSET(  __u8, UART, 0, IntVerify )#define H3800_ASIC2_UART_0_FIFOControl      H3800_ASIC2_NOFFSET(  __u8, UART, 0, FIFOControl )#define H3800_ASIC2_UART_0_LineControl      H3800_ASIC2_NOFFSET(  __u8, UART, 0, LineControl )#define H3800_ASIC2_UART_0_ModemStatus      H3800_ASIC2_NOFFSET(  __u8, UART, 0, ModemStatus )#define H3800_ASIC2_UART_0_LineStatus       H3800_ASIC2_NOFFSET(  __u8, UART, 0, LineStatus )#define H3800_ASIC2_UART_0_ScratchPad       H3800_ASIC2_NOFFSET(  __u8, UART, 0, ScratchPad )#define H3800_ASIC2_UART_0_DivisorLatchL    H3800_ASIC2_NOFFSET(  __u8, UART, 0, DivisorLatchL )#define H3800_ASIC2_UART_0_DivisorLatchH    H3800_ASIC2_NOFFSET(  __u8, UART, 0, DivisorLatchH )#define H3800_ASIC2_UART_1_Receive          H3800_ASIC2_NOFFSET(  __u8, UART, 1, Receive )#define H3800_ASIC2_UART_1_Transmit         H3800_ASIC2_NOFFSET(  __u8, UART, 1, Transmit )#define H3800_ASIC2_UART_1_IntEnable        H3800_ASIC2_NOFFSET(  __u8, UART, 1, IntEnable )#define H3800_ASIC2_UART_1_IntVerify        H3800_ASIC2_NOFFSET(  __u8, UART, 1, IntVerify )#define H3800_ASIC2_UART_1_FIFOControl      H3800_ASIC2_NOFFSET(  __u8, UART, 1, FIFOControl )#define H3800_ASIC2_UART_1_LineControl      H3800_ASIC2_NOFFSET(  __u8, UART, 1, LineControl )#define H3800_ASIC2_UART_1_ModemStatus      H3800_ASIC2_NOFFSET(  __u8, UART, 1, ModemStatus )#define H3800_ASIC2_UART_1_LineStatus       H3800_ASIC2_NOFFSET(  __u8, UART, 1, LineStatus )#define H3800_ASIC2_UART_1_ScratchPad       H3800_ASIC2_NOFFSET(  __u8, UART, 1, ScratchPad )#define H3800_ASIC2_UART_1_DivisorLatchL    H3800_ASIC2_NOFFSET(  __u8, UART, 1, DivisorLatchL )#define H3800_ASIC2_UART_1_DivisorLatchH    H3800_ASIC2_NOFFSET(  __u8, UART, 1, DivisorLatchH )#define _H3800_ASIC2_TIMER_Base                0x0E00#define _H3800_ASIC2_TIMER_Command             0x0000    /* R/W  8 bits */#define H3800_ASIC2_TIMER_Command           H3800_ASIC2_OFFSET( __u8, Timer, Command )#define H3800_ASIC2_TIMER_GAT_0            ( 1 << 0 )    /* Gate enable, counter 0 */#define H3800_ASIC2_TIMER_GAT_1            ( 1 << 1 )    /* Gate enable, counter 1 */#define H3800_ASIC2_TIMER_GAT_2            ( 1 << 2 )    /* Gate enable, counter 2 */#define H3800_ASIC2_TIMER_CLK_0            ( 1 << 3 )    /* Clock enable, counter 0 */#define H3800_ASIC2_TIMER_CLK_1            ( 1 << 4 )    /* Clock enable, counter 1 */#define H3800_ASIC2_TIMER_CLK_2            ( 1 << 5 )    /* Clock enable, counter 2 */#define H3800_ASIC2_TIMER_MODE_0           ( 1 << 6 )    /* Mode 0 enable, counter 0 */#define H3800_ASIC2_TIMER_MODE_1           ( 1 << 7 )    /* Mode 0 enable, counter 1 */#define _H3800_ASIC2_CLOCK_Base                0x1000#define _H3800_ASIC2_CLOCK_Enable              0x0000    /* R/W  18 bits */#define H3800_ASIC2_CLOCK_Enable            H3800_ASIC2_OFFSET( __u32, CLOCK, Enable )#define H3800_ASIC2_CLOCK_AUDIO_1              0x0001    /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */#define H3800_ASIC2_CLOCK_AUDIO_2              0x0002    /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */#define H3800_ASIC2_CLOCK_AUDIO_3              0x0004    /* Enable 5.6 MHz clock for 11 kHZ sample rate */#define H3800_ASIC2_CLOCK_AUDIO_4              0x0008    /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */#define H3800_ASIC2_CLOCK_ADC              ( 1 << 4 )    /* 1.024 MHz clock to ADC */#define H3800_ASIC2_CLOCK_SPI              ( 1 << 5 )    /* 4.096 MHz clock to SPI */#define H3800_ASIC2_CLOCK_OWM              ( 1 << 6 )    /* 4.096 MHz clock to OWM */#define H3800_ASIC2_CLOCK_PWM              ( 1 << 7 )    /* 2.048 MHz clock to PWM */#define H3800_ASIC2_CLOCK_UART_1           ( 1 << 8 )    /* 24.576 MHz clock to UART1 (turn off bit 16) */#define H3800_ASIC2_CLOCK_UART_0           ( 1 << 9 )    /* 24.576 MHz clock to UART0 (turn off bit 17) */#define H3800_ASIC2_CLOCK_SD_1             ( 1 << 10 )   /* 16.934 MHz to SD */#define H3800_ASIC2_CLOCK_SD_2             ( 2 << 10 )   /* 24.576 MHz to SD */#define H3800_ASIC2_CLOCK_SD_3             ( 3 << 10 )   /* 33.869 MHz to SD */#define H3800_ASIC2_CLOCK_SD_4             ( 4 << 10 )   /* 49.152 MHz to SD */#define H3800_ASIC2_CLOCK_EX0              ( 1 << 13 )   /* Enable 32.768 kHz crystal */#define H3800_ASIC2_CLOCK_EX1              ( 1 << 14 )   /* Enable 24.576 MHz crystal */#define H3800_ASIC2_CLOCK_EX2              ( 1 << 15 )   /* Enable 33.869 MHz crystal */#define H3800_ASIC2_CLOCK_SLOW_UART_1      ( 1 << 16 )   /* Enable 3.686 MHz to UART1 (turn off bit 8) */#define H3800_ASIC2_CLOCK_SLOW_UART_0      ( 1 << 17 )   /* Enable 3.686 MHz to UART0 (turn off bit 9) */#define _H3800_ASIC2_ADC_Base                  0x1200#define _H3800_ASIC2_ADC_Multiplexer           0x0000    /* R/W 4 bits - low 3 bits set channel */#define _H3800_ASIC2_ADC_ControlStatus         0x0004    /* R/W 8 bits */#define _H3800_ASIC2_ADC_Data                  0x0008    /* R   10 bits */#define H3800_ASIC2_ADC_Multiplexer       H3800_ASIC2_OFFSET(  __u8, ADC, Multiplexer )#define H3800_ASIC2_ADC_ControlStatus     H3800_ASIC2_OFFSET(  __u8, ADC, ControlStatus )#define H3800_ASIC2_ADC_Data              H3800_ASIC2_OFFSET( __u16, ADC, Data )#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK         0x07    /* Low 3 bits sets channel.  max = 4 */#define H3600_ASIC2_ADC_MUX_CLKEN          ( 1 << 3 )    /* Enable clock */#define H3600_ASIC2_ADC_CSR_ADPS_MASK            0x0f    /* Low 4 bits sets prescale, max = 8 */#define H3600_ASIC2_ADC_CSR_FREE_RUN       ( 1 << 4 )#define H3600_ASIC2_ADC_CSR_INT_ENABLE     ( 1 << 5 )#define H3600_ASIC2_ADC_CSR_START          ( 1 << 6 )    /* Set to start conversion.  Goes to 0 when done */#define H3600_ASIC2_ADC_CSR_ENABLE         ( 1 << 7 )    /* 1:power up ADC, 0:power down */#define _H3800_ASIC2_INTR_Base                 0x1600#define _H3800_ASIC2_INTR_MaskAndFlag          0x0000    /* R/(W) 8bits */#define _H3800_ASIC2_INTR_ClockPrescale        0x0004    /* R/(W) 5bits */#define _H3800_ASIC2_INTR_TimerSet             0x0008    /* R/(W) 8bits */#define H3800_ASIC2_INTR_MaskAndFlag      H3800_ASIC2_OFFSET( __u8, INTR, MaskAndFlag )#define H3800_ASIC2_INTR_ClockPrescale    H3800_ASIC2_OFFSET( __u8, INTR, ClockPrescale )#define H3800_ASIC2_INTR_TimerSet         H3800_ASIC2_OFFSET( __u8, INTR, TimerSet )#define H3800_ASIC2_INTR_GLOBAL_MASK       ( 1 << 0 )    /* Global interrupt mask */#define H3800_ASIC2_INTR_POWER_ON_RESET    ( 1 << 1 )    /* 01: Power on reset (bits 1 & 2 ) */#define H3800_ASIC2_INTR_EXTERNAL_RESET    ( 2 << 1 )    /* 10: External reset (bits 1 & 2 ) */#define H3800_ASIC2_INTR_MASK_UART_0       ( 1 << 4 )#define H3800_ASIC2_INTR_MASK_UART_1       ( 1 << 5 )#define H3800_ASIC2_INTR_MASK_TIMER        ( 1 << 6 )#define H3800_ASIC2_INTR_MASK_OWM          ( 1 << 7 )#define H3800_ASIC2_INTR_CLOCK_PRESCALE          0x0f    /* 4 bits, max 14 */#define H3800_ASIC2_INTR_SET               ( 1 << 4 )    /* Time base enable */#define _H3800_ASIC2_OWM_Base                  0x1800#define _H3800_ASIC2_OWM_Command               0x0000    /* R/W 4 bits command register */#define _H3800_ASIC2_OWM_Data                  0x0004    /* R/W 8 bits, transmit / receive buffer */#define _H3800_ASIC2_OWM_Interrupt             0x0008    /* R/W Command register */#define _H3800_ASIC2_OWM_InterruptEnable       0x000c    /* R/W Command register */#define _H3800_ASIC2_OWM_ClockDivisor          0x0010    /* R/W 5 bits of divisor and pre-scale */#define H3800_ASIC2_OWM_Command            H3800_ASIC2_OFFSET( __u8, OWM, Command )