#define H3800_ASIC2_OWM_Data               H3800_ASIC2_OFFSET( __u8, OWM, Data )#define H3800_ASIC2_OWM_Interrupt          H3800_ASIC2_OFFSET( __u8, OWM, Interrupt )#define H3800_ASIC2_OWM_InterruptEnable    H3800_ASIC2_OFFSET( __u8, OWM, InterruptEnable )#define H3800_ASIC2_OWM_ClockDivisor       H3800_ASIC2_OFFSET( __u8, OWM, ClockDivisor )#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 )    /* Set to force reset on 1-wire bus */#define H3800_ASIC2_OWM_CMD_SRA            ( 1 << 1 )    /* Set to switch to Search ROM accelerator mode */#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT      ( 1 << 2 )    /* Write only - forces bus low */#define H3800_ASIC2_OWM_CMD_DQ_INPUT       ( 1 << 3 )    /* Read only - reflects state of bus */#define H3800_ASIC2_OWM_INT_PD             ( 1 << 0 )    /* Presence detect */#define H3800_ASIC2_OWM_INT_PDR            ( 1 << 1 )    /* Presence detect result */#define H3800_ASIC2_OWM_INT_TBE            ( 1 << 2 )    /* Transmit buffer empty */#define H3800_ASIC2_OWM_INT_TEMT           ( 1 << 3 )    /* Transmit shift register empty */#define H3800_ASIC2_OWM_INT_RBF            ( 1 << 4 )    /* Receive buffer full */#define H3800_ASIC2_OWM_INTEN_EPD          ( 1 << 0 )    /* Enable receive buffer full interrupt */#define H3800_ASIC2_OWM_INTEN_IAS          ( 1 << 1 )    /* Enable transmit shift register empty interrupt */#define H3800_ASIC2_OWM_INTEN_ETBE         ( 1 << 2 )    /* Enable transmit buffer empty interrupt */#define H3800_ASIC2_OWM_INTEN_ETMT         ( 1 << 3 )    /* INTR active state */#define H3800_ASIC2_OWM_INTEN_ERBF         ( 1 << 4 )    /* Enable presence detect interrupt */#define _H3800_ASIC2_FlashCtl_Base             0x1A00/****************************************************//* H3800, ASIC #1 * This ASIC is accesed through ASIC #2, and * mapped into the 1c00 - 1f00 region */#define H3800_ASIC1_OFFSET(s,x,y)   \     (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))#define _H3800_ASIC1_MMC_Base             0x1c00#define _H3800_ASIC1_MMC_StartStopClock     0x00    /* R/W 8bit                                  */#define _H3800_ASIC1_MMC_Status             0x02    /* R   See below, default 0x0040             */#define _H3800_ASIC1_MMC_ClockRate          0x04    /* R/W 8bit, low 3 bits are clock divisor    */#define _H3800_ASIC1_MMC_SPIRegister        0x08    /* R/W 8bit, see below                       */#define _H3800_ASIC1_MMC_CmdDataCont        0x0a    /* R/W 8bit, write to start MMC adapter      */#define _H3800_ASIC1_MMC_ResponseTimeout    0x0c    /* R/W 8bit, clocks before response timeout  */#define _H3800_ASIC1_MMC_ReadTimeout        0x0e    /* R/W 16bit, clocks before received data timeout */#define _H3800_ASIC1_MMC_BlockLength        0x10    /* R/W 10bit */#define _H3800_ASIC1_MMC_NumOfBlocks        0x12    /* R/W 16bit, in block mode, number of blocks  */#define _H3800_ASIC1_MMC_InterruptMask      0x1a    /* R/W 8bit */#define _H3800_ASIC1_MMC_CommandNumber      0x1c    /* R/W 6 bits */#define _H3800_ASIC1_MMC_ArgumentH          0x1e    /* R/W 16 bits  */#define _H3800_ASIC1_MMC_ArgumentL          0x20    /* R/W 16 bits */#define _H3800_ASIC1_MMC_ResFifo            0x22    /* R   8 x 16 bits - contains response FIFO */#define _H3800_ASIC1_MMC_BufferPartFull     0x28    /* R/W 8 bits */#define H3800_ASIC1_MMC_StartStopClock    H3800_ASIC1_OFFSET(  __u8, MMC, StartStopClock )#define H3800_ASIC1_MMC_Status            H3800_ASIC1_OFFSET( __u16, MMC, Status )#define H3800_ASIC1_MMC_ClockRate         H3800_ASIC1_OFFSET(  __u8, MMC, ClockRate )#define H3800_ASIC1_MMC_SPIRegister       H3800_ASIC1_OFFSET(  __u8, MMC, SPIRegister )#define H3800_ASIC1_MMC_CmdDataCont       H3800_ASIC1_OFFSET(  __u8, MMC, CmdDataCont )#define H3800_ASIC1_MMC_ResponseTimeout   H3800_ASIC1_OFFSET(  __u8, MMC, ResponseTimeout )#define H3800_ASIC1_MMC_ReadTimeout       H3800_ASIC1_OFFSET( __u16, MMC, ReadTimeout )#define H3800_ASIC1_MMC_BlockLength       H3800_ASIC1_OFFSET( __u16, MMC, BlockLength )#define H3800_ASIC1_MMC_NumOfBlocks       H3800_ASIC1_OFFSET( __u16, MMC, NumOfBlocks )#define H3800_ASIC1_MMC_InterruptMask     H3800_ASIC1_OFFSET(  __u8, MMC, InterruptMask )#define H3800_ASIC1_MMC_CommandNumber     H3800_ASIC1_OFFSET(  __u8, MMC, CommandNumber )#define H3800_ASIC1_MMC_ArgumentH         H3800_ASIC1_OFFSET( __u16, MMC, ArgumentH )#define H3800_ASIC1_MMC_ArgumentL         H3800_ASIC1_OFFSET( __u16, MMC, ArgumentL )#define H3800_ASIC1_MMC_ResFifo           H3800_ASIC1_OFFSET( __u16, MMC, ResFifo )#define H3800_ASIC1_MMC_BufferPartFull    H3800_ASIC1_OFFSET(  __u8, MMC, BufferPartFull )#define H3800_ASIC1_MMC_STOP_CLOCK                   (1 << 0)   /* Write to "StartStopClock" register */#define H3800_ASIC1_MMC_START_CLOCK                  (1 << 1)#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT          (1 << 0)#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT      (1 << 1)#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR       (1 << 2)#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR        (1 << 3)#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR        (1 << 4)  /* SPI data token error received */#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR    (1 << 5)#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY            (1 << 6)#define H3800_ASIC1_MMC_STATUS_FIFO_FULL             (1 << 7)#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE          (1 << 8)  /* MultiMediaCard clock stopped */#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE    (1 << 11) /* Write operation, indicates transfer finished */#define H3800_ASIC1_MMC_STATUS_END_PROGRAM           (1 << 12) /* End write and read operations */#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE  (1 << 13) /* End command response */#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE           (1 << 0)  /* Enables SPI mode */#define H3800_ASIC1_MMC_SPI_REG_CRC_ON               (1 << 1)  /* 1:turn on CRC    */#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE        (1 << 2)  /* 1:turn on SPI CS */#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK      0x38      /* Bits 3,4,5 are the SPI CS relative address */#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE  0x00#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1           0x01#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2           0x02#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3           0x03#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE         (1 << 2)  /* This command contains a data transfer */#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE               (1 << 3)  /* This data transfer is a write */#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE         (1 << 4)  /* This data transfer is in stream mode */#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT            (1 << 5)  /* Busy signal expected after current cmd */#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE          (1 << 6)  /* Enables the 80 bits for initializing card */#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE       (1 << 0)#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE             (1 << 1)#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE     (1 << 2)#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY             (1 << 3)#define H3800_ASIC1_MMC_BUFFER_PART_FULL                  (1 << 0)/********* GPIO **********/#define _H3800_ASIC1_GPIO_Base        0x1e00#define _H3800_ASIC1_GPIO_Mask          0x30    /* R/W 0:don't mask, 1:mask interrupt */#define _H3800_ASIC1_GPIO_Direction     0x32    /* R/W 0:input, 1:output              */#define _H3800_ASIC1_GPIO_Out           0x34    /* R/W 0:output low, 1:output high    */#define _H3800_ASIC1_GPIO_TriggerType   0x36    /* R/W 0:level, 1:edge                */#define _H3800_ASIC1_GPIO_EdgeTrigger   0x38    /* R/W 0:falling, 1:rising            */#define _H3800_ASIC1_GPIO_LevelTrigger  0x3A    /* R/W 0:low, 1:high level detect     */#define _H3800_ASIC1_GPIO_LevelStatus   0x3C    /* R/W 0:none, 1:detect               */#define _H3800_ASIC1_GPIO_EdgeStatus    0x3E    /* R/W 0:none, 1:detect               */#define _H3800_ASIC1_GPIO_State         0x40    /* R   See masks below  (default 0)         */#define _H3800_ASIC1_GPIO_Reset         0x42    /* R/W See masks below  (default 0x04)      */#define _H3800_ASIC1_GPIO_SleepMask     0x44    /* R/W 0:don't mask, 1:mask trigger in sleep mode  */#define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:output in sleep mode    */#define _H3800_ASIC1_GPIO_SleepOut      0x48    /* R/W level 0:low, 1:high in sleep mode           */#define _H3800_ASIC1_GPIO_Status        0x4A    /* R   Pin status                                  */#define _H3800_ASIC1_GPIO_BattFaultDir  0x4C    /* R/W direction 0:input, 1:output in batt_fault   */#define _H3800_ASIC1_GPIO_BattFaultOut  0x4E    /* R/W level 0:low, 1:high in batt_fault           */#define H3800_ASIC1_GPIO_Mask         H3800_ASIC1_OFFSET( __u16, GPIO, Mask )#define H3800_ASIC1_GPIO_Direction    H3800_ASIC1_OFFSET( __u16, GPIO, Direction )#define H3800_ASIC1_GPIO_Out          H3800_ASIC1_OFFSET( __u16, GPIO, Out )#define H3800_ASIC1_GPIO_TriggerType  H3800_ASIC1_OFFSET( __u16, GPIO, TriggerType )#define H3800_ASIC1_GPIO_EdgeTrigger  H3800_ASIC1_OFFSET( __u16, GPIO, EdgeTrigger )#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( __u16, GPIO, LevelTrigger )#define H3800_ASIC1_GPIO_LevelStatus  H3800_ASIC1_OFFSET( __u16, GPIO, LevelStatus )#define H3800_ASIC1_GPIO_EdgeStatus   H3800_ASIC1_OFFSET( __u16, GPIO, EdgeStatus )#define H3800_ASIC1_GPIO_State        H3800_ASIC1_OFFSET(  __u8, GPIO, State )#define H3800_ASIC1_GPIO_Reset        H3800_ASIC1_OFFSET(  __u8, GPIO, Reset )#define H3800_ASIC1_GPIO_SleepMask    H3800_ASIC1_OFFSET( __u16, GPIO, SleepMask )#define H3800_ASIC1_GPIO_SleepDir     H3800_ASIC1_OFFSET( __u16, GPIO, SleepDir )#define H3800_ASIC1_GPIO_SleepOut     H3800_ASIC1_OFFSET( __u16, GPIO, SleepOut )#define H3800_ASIC1_GPIO_Status       H3800_ASIC1_OFFSET( __u16, GPIO, Status )#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( __u16, GPIO, BattFaultDir )#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( __u16, GPIO, BattFaultOut )#define H3800_ASIC1_GPIO_STATE_MASK            (1 << 0)#define H3800_ASIC1_GPIO_STATE_DIRECTION       (1 << 1)#define H3800_ASIC1_GPIO_STATE_OUT             (1 << 2)#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE    (1 << 3)#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER    (1 << 4)#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER   (1 << 5)#define H3800_ASIC1_GPIO_RESET_SOFTWARE        (1 << 0)#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP      (1 << 1)#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON    (1 << 2)/* These are all outputs */#define GPIO_H3800_ASIC1_IR_ON_N          (1 << 0)   /* Apply power to the IR Module */#define GPIO_H3800_ASIC1_SD_PWR_ON        (1 << 1)   /* Secure Digital power on */#define GPIO_H3800_ASIC1_RS232_ON         (1 << 2)   /* Turn on power to the RS232 chip ? */#define GPIO_H3800_ASIC1_PULSE_GEN        (1 << 3)   /* Goes to speaker / earphone */#define GPIO_H3800_ASIC1_CH_TIMER         (1 << 4)   /* */#define GPIO_H3800_ASIC1_LCD_5V_ON        (1 << 5)   /* Enables LCD_5V */#define GPIO_H3800_ASIC1_LCD_ON           (1 << 6)   /* Enables LCD_3V */#define GPIO_H3800_ASIC1_LCD_PCI          (1 << 7)   /* Connects to PDWN on LCD controller */#define GPIO_H3800_ASIC1_VGH_ON           (1 << 8)   /* Drives VGH on the LCD (+9??) */#define GPIO_H3800_ASIC1_VGL_ON           (1 << 9)   /* Drivers VGL on the LCD (-6??) */#define GPIO_H3800_ASIC1_FL_PWR_ON        (1 << 10)  /* Frontlight power on */#define GPIO_H3800_ASIC1_BT_PWR_ON        (1 << 11)  /* Bluetooth power on */#define GPIO_H3800_ASIC1_SPK_ON           (1 << 12)  /* */#define GPIO_H3800_ASIC1_EAR_ON_N         (1 << 13)  /* */#define GPIO_H3800_ASIC1_AUD_PWR_ON       (1 << 14)  /* *//* Write enable for the flash */#define _H3800_ASIC1_FlashWP_Base         0x1F00#define _H3800_ASIC1_FlashWP_VPP_ON         0x00    /* R   1: write, 0: protect */#define H3800_ASIC1_FlashWP_VPP_ON       H3800_ASIC1_OFFSET( __u8, FlashWP, VPP_ON )#endif /* _INCLUDE_H3600_GPIO_H_ */