/* * Synchronous Serial Port (SSP) control registers * * Registers *    Ser4SSCR0 	Serial port 4 Synchronous Serial Port (SSP) Control *              	Register 0 (read/write). *    Ser4SSCR1 	Serial port 4 Synchronous Serial Port (SSP) Control *              	Register 1 (read/write). *              	[Bits SPO and SP are only implemented in versions 2.0 *              	(rev. = 8) and higher of the StrongARM SA-1100.] *    Ser4SSDR  	Serial port 4 Synchronous Serial Port (SSP) Data *              	Register (read/write). *    Ser4SSSR  	Serial port 4 Synchronous Serial Port (SSP) Status *              	Register (read/write). * * Clocks *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz *              	or 3.5795 MHz). *    fss, Tss  	Frequency, period of the SSP communication. */#define Ser4SSCR0	__REG(0x80070060)  /* Ser. port 4 SSP Control Reg. 0 */#define Ser4SSCR1	__REG(0x80070064)  /* Ser. port 4 SSP Control Reg. 1 */#define Ser4SSDR	__REG(0x8007006C)  /* Ser. port 4 SSP Data Reg. */#define Ser4SSSR	__REG(0x80070074)  /* Ser. port 4 SSP Status Reg. */#define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */#define SSCR0_DataSize(Size)    	/*  Data Size Select [4..16]       */ \                	(((Size) - 1) << FShft (SSCR0_DSS))#define SSCR0_FRF	Fld (2, 4)	/* FRame Format                    */#define SSCR0_Motorola	        	/*  Motorola Serial Peripheral     */ \                	        	/*  Interface (SPI) format         */ \                	(0 << FShft (SSCR0_FRF))#define SSCR0_TI	        	/*  Texas Instruments Synchronous  */ \                	        	/*  Serial format                  */ \                	(1 << FShft (SSCR0_FRF))#define SSCR0_National	        	/*  National Microwire format      */ \                	(2 << FShft (SSCR0_FRF))#define SSCR0_SSE	0x00000080	/* SSP Enable                      */#define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */                	        	/* fss = fxtl/(2*(SCR + 1))        */                	        	/* Tss = 2*(SCR + 1)*Txtl          */#define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \                	(((Div) - 2)/2 << FShft (SSCR0_SCR))                	        	/*  fss = fxtl/(2*Floor (Div/2))   */                	        	/*  Tss = 2*Floor (Div/2)*Txtl     */#define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \                	(((Div) - 1)/2 << FShft (SSCR0_SCR))                	        	/*  fss = fxtl/(2*Ceil (Div/2))    */                	        	/*  Tss = 2*Ceil (Div/2)*Txtl      */#define SSCR1_RIE	0x00000001	/* Receive FIFO 1/2-full or more   */                	        	/* Interrupt Enable                */#define SSCR1_TIE	0x00000002	/* Transmit FIFO 1/2-full or less  */                	        	/* Interrupt Enable                */#define SSCR1_LBM	0x00000004	/* Look-Back Mode                  */#define SSCR1_SPO	0x00000008	/* Sample clock (SCLK) POlarity    */#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low      */#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High     */#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase       */#define SSCR1_SClk1P	(SSCR1_SP*0)	/*  Sample Clock active 1 Period   */                	        	/*  after frame (SFRM, 1st edge)   */#define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */                	        	/*  after frame (SFRM, 1st edge)   */#define SSCR1_ECS	0x00000020	/* External Clock Select           */#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock                 */#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])     */#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs     */#define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */#define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */#define SSSR_BSY	0x00000008	/* SSP BuSY (read)                 */#define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */                	        	/* Service request (read)          */#define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */                	        	/* Service request (read)          */#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run           *//* * Operating System (OS) timer control registers * * Registers *    OSMR0     	Operating System (OS) timer Match Register 0 *              	(read/write). *    OSMR1     	Operating System (OS) timer Match Register 1 *              	(read/write). *    OSMR2     	Operating System (OS) timer Match Register 2 *              	(read/write). *    OSMR3     	Operating System (OS) timer Match Register 3 *              	(read/write). *    OSCR      	Operating System (OS) timer Counter Register *              	(read/write). *    OSSR      	Operating System (OS) timer Status Register *              	(read/write). *    OWER      	Operating System (OS) timer Watch-dog Enable Register *              	(read/write). *    OIER      	Operating System (OS) timer Interrupt Enable Register *              	(read/write). */#define OSMR0  		__REG(0x90000000)  /* OS timer Match Reg. 0 */#define OSMR1  		__REG(0x90000004)  /* OS timer Match Reg. 1 */#define OSMR2  		__REG(0x90000008)  /* OS timer Match Reg. 2 */#define OSMR3  		__REG(0x9000000c)  /* OS timer Match Reg. 3 */#define OSCR   	__REG(0x90000010)  /* OS timer Counter Reg. */#define OSSR   	__REG(0x90000014	)  /* OS timer Status Reg. */#define OWER   	__REG(0x90000018	)  /* OS timer Watch-dog Enable Reg. */#define OIER   	__REG(0x9000001C	)  /* OS timer Interrupt Enable Reg. */#define OSSR_M(Nb)	        	/* Match detected [0..3]           */ \                	(0x00000001 << (Nb))#define OSSR_M0 	OSSR_M (0)	/* Match detected 0                */#define OSSR_M1 	OSSR_M (1)	/* Match detected 1                */#define OSSR_M2 	OSSR_M (2)	/* Match detected 2                */#define OSSR_M3 	OSSR_M (3)	/* Match detected 3                */#define OWER_WME	0x00000001	/* Watch-dog Match Enable          */                	        	/* (set only)                      */#define OIER_E(Nb)	        	/* match interrupt Enable [0..3]   */ \                	(0x00000001 << (Nb))#define OIER_E0 	OIER_E (0)	/* match interrupt Enable 0        */#define OIER_E1 	OIER_E (1)	/* match interrupt Enable 1        */#define OIER_E2 	OIER_E (2)	/* match interrupt Enable 2        */#define OIER_E3 	OIER_E (3)	/* match interrupt Enable 3        *//* * Real-Time Clock (RTC) control registers * * Registers *    RTAR      	Real-Time Clock (RTC) Alarm Register (read/write). *    RCNR      	Real-Time Clock (RTC) CouNt Register (read/write). *    RTTR      	Real-Time Clock (RTC) Trim Register (read/write). *    RTSR      	Real-Time Clock (RTC) Status Register (read/write). * * Clocks *    frtx, Trtx	Frequency, period of the real-time clock crystal *              	(32.768 kHz nominal). *    frtc, Trtc	Frequency, period of the real-time clock counter *              	(1 Hz nominal). */#define RTAR		__REG(0x90010000)  /* RTC Alarm Reg. */#define RCNR		__REG(0x90010004)  /* RTC CouNt Reg. */#define RTTR		__REG(0x90010008)  /* RTC Trim Reg. */#define RTSR		__REG(0x90010010)  /* RTC Status Reg. */#define RTTR_C  	Fld (16, 0)	/* clock divider Count - 1         */#define RTTR_D  	Fld (10, 16)	/* trim Delete count               */                	        	/* frtc = (1023*(C + 1) - D)*frtx/ */                	        	/*        (1023*(C + 1)^2)         */                	        	/* Trtc = (1023*(C + 1)^2)*Trtx/   */                	        	/*        (1023*(C + 1) - D)       */#define RTSR_AL 	0x00000001	/* ALarm detected                  */#define RTSR_HZ 	0x00000002	/* 1 Hz clock detected             */#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable          */#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable     *//* * Power Manager (PM) control registers * * Registers *    PMCR      	Power Manager (PM) Control Register (read/write). *    PSSR      	Power Manager (PM) Sleep Status Register (read/write). *    PSPR      	Power Manager (PM) Scratch-Pad Register (read/write). *    PWER      	Power Manager (PM) Wake-up Enable Register *              	(read/write). *    PCFR      	Power Manager (PM) general ConFiguration Register *              	(read/write). *    PPCR      	Power Manager (PM) Phase-Locked Loop (PLL) *              	Configuration Register (read/write). *    PGSR      	Power Manager (PM) General-Purpose Input/Output (GPIO) *              	Sleep state Register (read/write, see GPIO pins). *    POSR      	Power Manager (PM) Oscillator Status Register (read). * * Clocks *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz *              	or 3.5795 MHz). *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK). */#define PMCR		__REG(0x90020000)  /* PM Control Reg. */#define PSSR		__REG(0x90020004)  /* PM Sleep Status Reg. */#define PSPR		__REG(0x90020008)  /* PM Scratch-Pad Reg. */#define PWER		__REG(0x9002000C)  /* PM Wake-up Enable Reg. */#define PCFR		__REG(0x90020010)  /* PM general ConFiguration Reg. */#define PPCR		__REG(0x90020014)  /* PM PLL Configuration Reg. */#define PGSR		__REG(0x90020018)  /* PM GPIO Sleep state Reg. */#define POSR		__REG(0x9002001C)  /* PM Oscillator Status Reg. */#define PMCR_SF 	0x00000001	/* Sleep Force (set only)          */#define PSSR_SS 	0x00000001	/* Software Sleep                  */#define PSSR_BFS	0x00000002	/* Battery Fault Status            */                	        	/* (BATT_FAULT)                    */#define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */#define PSSR_DH 	0x00000008	/* DRAM control Hold               */#define PSSR_PH 	0x00000010	/* Peripheral control Hold         */#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable     */#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable        */#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable        */#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable        */#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable        */#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable        */#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable        */#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable        */#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable        */#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable        */#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable        */#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable        */#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable        */#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */#define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */#define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */#define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */#define PCFR_FP 	0x00000002	/* Float PCMCIA pins               */#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)        */#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating           */#define PCFR_FS 	0x00000004	/* Float Static memory pins        */