/*
;********************************************************************************************************
;                                               uC/CPU
;                                    CPU CONFIGURATION & PORT LAYER
;
;                          (c) Copyright 2004-2006; Micrium, Inc.; Weston, FL
;
;               All rights reserved.  Protected by international copyright laws.
;
;               uC/CPU is provided in source form for FREE evaluation, for educational
;               use or peaceful research.  If you plan on using uC/CPU in a commercial
;               product you need to contact Micrium to properly license its use in your
;               product.  We provide ALL the source code for your convenience and to
;               help you experience uC/CPU.  The fact that the source code is provided
;               does NOT mean that you can use it without paying a licensing fee.
;
;               Knowledge of the source code may NOT be used to develop a similar product.
;
;               Please help us continue to provide the Embedded community with the finest
;               software available.  Your honesty is greatly appreciated.
;********************************************************************************************************
*/

/*
;********************************************************************************************************
;                                              ColdFire MCF51QE
;
; Filename      : cpu_a.asm
; Version       : V1.00
; Programmer(s) : EHS
;********************************************************************************************************
*/

/*
;*************************************************************************************************
;                                        PUBLIC DECLARATIONS
;*************************************************************************************************
*/

        .global  _CPU_SR_Save
        .global  _CPU_SR_Restore

        .text

/*
;********************************************************************************************************
;                              CPU_SR_Save() for OS_CRITICAL_METHOD #3
;
; Description : This functions implements the OS_CRITICAL_METHOD #3 function to preserve the state of the 
;               interrupt disable flag in order to be able to restore it later.
;
; Arguments   : none
;
; Returns     : It is assumed that the return value is placed in the D0 register as expected by the
;               compiler.
;********************************************************************************************************
*/

_CPU_SR_Save:
        MOVE.W   SR,D0            ; Copy SR into D0 
        MOVE.L   D0,-(A7)         ; Save D0
        ORI.L    #0x0700,D0       ; Disable interrupts
        MOVE     D0,SR
        MOVE.L   (A7)+,D0         ; Restore D0
        RTS

/*
;********************************************************************************************************
;                              CPU_SR_Restore() for OS_CRITICAL_METHOD #3
;
; Description : This functions implements the OS_CRITICAL_METHOD #3 function to restore the state of the
;               interrupt flag.
;
; Arguments   : os_cpu_sr   is the contents of the SR to restore.  It is assumed that this 'argument' is 
;                           passed on the stack as follows:
;
;               A7 +  0 ->  D0
;                  +  4     return address
;                  +  8     return address
;                  +  4     D0
;               A7 +  0 ->
;
; Returns     : None 
;********************************************************************************************************
*/

_CPU_SR_Restore:
        MOVE.L   D0,-(A7)         ; Save D0
        MOVE.W   10(A7),D0
        MOVE.W    D0,SR
        MOVE.L   (A7)+,D0         ; Restore D0
        RTS