?? dsasm_functions.cpp
字號:
else
{ // Extension==0
SwapWord((BYTE*)(*Opcode+pos+1),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(temp,"%02X",FOpcode);
lstrcat((*Disasm)->Opcode,temp);
}
}
strcpy(Aritmathic,"");
if(Op==0x82 || Op==0x83)
if(FOpcode>0x7F) // check for signed numbers
{
wsprintf(Aritmathic,"%s",Scale[0]); // '-' Signed Numbers
FOpcode = 0x100-FOpcode; // -XX (Negative the Number)
}
// Check Opcode
if(Op==0xC6)
{
/*
Instruction rule: Mem,Imm -> 1100011woo000mmm,imm
Code Block: 1100011
w = Reg Size
oo - Mod
000 - Must be!
mmm - Reg/Mem
imm - Immidiant (麼弳)
*/
// Check valid Opcode, must have 000 bit
if(reg1!=0)
lstrcat( (*Disasm)->Remarks,"Invalid Instruction!");
// Instruction
wsprintf(instruction,"%s","mov");
}
else
wsprintf(instruction,"%s",Instructions[REG]);
wsprintf(temp,"%s %s,%s%02X",instruction,tempMeme,Aritmathic,FOpcode);
(*(*index))++;
(*Disasm)->OpcodeSize++;
}
break;
case 0x8C: // Segments in Source Register
{
wsprintf(temp,"%s %s,%s",instruction,tempMeme,segs[REG]);
}
break;
case 0xD0: case 0xD1:
{
wsprintf(temp,"%s %s,1",ArtimaticInstructions[REG],tempMeme);
}
break;
case 0xD2: case 0xD3:
{
wsprintf(temp,"%s %s,cl",ArtimaticInstructions[REG],tempMeme);
}
break;
case 0xD8: case 0xDC:// Unsigned FPU Instructions (unsigned)
{
wsprintf(temp,"%s %s",FpuInstructions[REG],tempMeme);
}
break;
case 0xD9: // FPU Instructions Set2 (UnSigned)
{
if(REG==0 && reg1!=0) // (11011001oo[000]mmm) must have 00 else invalid! fld instruction only
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
else {
if(REG==1) // no such fpu instruction!
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
}
wsprintf(temp,"%s %s",FpuInstructionsSet2[REG],tempMeme);
}
break;
case 0xDA: case 0xDE:// FPU Instructions (Signed)
{
wsprintf(temp,"%s %s",FpuInstructionsSigned[REG],tempMeme);
}
break;
case 0xDB: // FPU Instructions Set2 (Signed)
{
if(REG==1 || REG==4 || REG==6) // No such fpu instructions!
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
wsprintf(temp,"%s %s",FpuInstructionsSet2Signed[REG],tempMeme);
}
break;
case 0xDD:// FPU Instructions Set2 (Signed)
{
if(REG==1 || REG==5) // no such fpu instruction!
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
wsprintf(temp,"%s %s",FpuInstructionsSet3[REG],tempMeme);
}
break;
case 0xDF: // Extended FPU Instructions Set2 (Signed)
{
if(REG==1) // no such fpu instruction!
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
wsprintf(temp,"%s %s",FpuInstructionsSet2Signed_EX[REG],tempMeme);
}
break;
case 0xF6:
{
// We check Extension because there is a diff
// Reading position of bytes depend on the extension
// 1 = read byte, 3rd position
// 2 = read dword, 6th position
if(Extension==1) // read 1 byte at 3rd position
{
SwapWord((BYTE*)(*Opcode+pos+2),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(temp,"%02X",FOpcode);
lstrcat((*Disasm)->Opcode,temp);
}
else{
if(Extension==2) //read byte at 7th position (dword read before)
{
SwapWord((BYTE*)(*Opcode+pos+4),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(temp,"%02X",FOpcode);
lstrcat((*Disasm)->Opcode,temp);
}
else
{ // Extension==0
SwapWord((BYTE*)(*Opcode+pos+1),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(temp,"%02X",FOpcode);
lstrcat((*Disasm)->Opcode,temp);
}
}
strcpy(Aritmathic,"");
wsprintf(instruction,"%s",InstructionsSet2[REG]);
if(reg1==0 || reg1==1)
{
wsprintf(temp,"%s %s,%s%02X",instruction,tempMeme,Aritmathic,FOpcode);
(*(*index))++;
(*Disasm)->OpcodeSize++;
}
else
wsprintf(temp,"%s %s",instruction,tempMeme);
}
break;
case 0xF7:
{
// get instruction
wsprintf(instruction,"%s",InstructionsSet2[REG]);
// Get Extensions!
//================
if(reg1==0 || reg1==1)
{
if(Extension==0)
{
if(PrefixReg==0)
{
SwapDword((BYTE*)(*Opcode+pos+2),&dwOp,&dwMem);
wsprintf(temp," %08X",dwOp);
lstrcat((*Disasm)->Opcode,temp);
wsprintf(temp,"%08X",dwMem);
}
else
{
SwapWord((BYTE*)(*Opcode+pos+2),&wOp,&wMem);
wsprintf(temp," %04X",wOp);
lstrcat((*Disasm)->Opcode,temp);
wsprintf(temp,"%04X",wMem);
}
}
else if(Extension==1)
{
if(PrefixReg==0)
{
SwapDword((BYTE*)(*Opcode+pos+3),&dwOp,&dwMem);
wsprintf(temp," %08X",dwOp);
lstrcat((*Disasm)->Opcode,temp);
wsprintf(temp,"%08X",dwMem);
}
else
{
SwapWord((BYTE*)(*Opcode+pos+3),&wOp,&wMem);
wsprintf(temp," %04X",wOp);
lstrcat((*Disasm)->Opcode,temp);
wsprintf(temp,"%04X",wMem);
}
}
else if(Extension==2)
{
if(PrefixReg==0)
{
SwapDword((BYTE*)(*Opcode+pos+4),&dwOp,&dwMem);
wsprintf(temp," %08X",dwOp);
lstrcat((*Disasm)->Opcode,temp);
wsprintf(temp,"%08X",dwMem);
}
else
{
SwapWord((BYTE*)(*Opcode+pos+4),&wOp,&wMem);
wsprintf(temp," %04X",wOp);
lstrcat((*Disasm)->Opcode,temp);
wsprintf(temp,"%04X",wMem);
}
}
wsprintf(menemonic,"%s %s,%s",instruction,tempMeme,temp);
(*(*index))+=4;
(*Disasm)->OpcodeSize+=4;
}
else
wsprintf(menemonic,"%s %s",instruction,tempMeme);
strcpy(temp,menemonic);
}
break;
case 0xFE: // MIX Instructions (INC,DEC,INVALID,INVALID,INVALID...)
{
wsprintf(temp,"%s %s",InstructionsSet3[REG],tempMeme);
if(REG>1) // Invalid instructions
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
}
break;
case 0xFF: // MIX Instructions (INC,DEC,CALL,PUSH,JMP,FAR JMP,FAR CALL,INVALID)
{
wsprintf(temp,"%s %s",InstructionsSet4[REG],tempMeme);
if(REG==3)// FAR CALL
{
lstrcat((*Disasm)->Remarks,"Far Call");
break;
}
if(REG==5) // FAR JUMP
{
lstrcat((*Disasm)->Remarks,"Far Jump");
break;
}
if(REG==7) // Invalid instructions
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
}
break;
default:
{
wsprintf(temp,"%s %s,%s",instruction,tempMeme,regs[RM][REG]);
}
break;
}
lstrcat((*Disasm)->Assembly,temp);
/*
wsprintf(menemonic,"%s %s,%s",instruction,tempMeme,regs[RM][REG]);
lstrcat((*Disasm)->Assembly,menemonic);
*/
}
break;
case 1: // (<-) Direction (Bit_D)
{
// Check Used Opcode Set
switch(Op)
{
case 0x8E:// Segments in Destination Register
{
wsprintf(menemonic,"%s %s,%s",instruction,segs[REG],tempMeme);
}
break;
// Mixed Bit Rotation Instructions (rol/ror/shl..)
case 0xC0: case 0xC1:
{
// Check Extension
switch(Extension)
{
case 0: // No Extension
{
SwapWord((BYTE*)(*Opcode+pos+1),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(menemonic,"%s %s,%02X",ArtimaticInstructions[REG],tempMeme,FOpcode);
wsprintf(tempMeme," %02X",FOpcode);
lstrcat((*Disasm)->Opcode,tempMeme);
(*(*index))++;
(*Disasm)->OpcodeSize++;
}
break;
case 1: // 1 byte Extension (Displacement)
{
SwapWord((BYTE*)(*Opcode+pos+2),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(menemonic,"%s %s,%02X",ArtimaticInstructions[REG],tempMeme,FOpcode);
wsprintf(tempMeme," %02X",FOpcode);
lstrcat((*Disasm)->Opcode,tempMeme);
(*(*index))++;
(*Disasm)->OpcodeSize++;
}
break;
case 2: // 2 Bytes Extension (Displacement)
{
SwapWord((BYTE*)(*Opcode+pos+3),&wOp,&wMem);
FOpcode=wOp&0x00FF;
wsprintf(menemonic,"%s %s,%02X",ArtimaticInstructions[REG],tempMeme,FOpcode);
wsprintf(tempMeme," %02X",FOpcode);
lstrcat((*Disasm)->Opcode,tempMeme);
(*(*index))++;
(*Disasm)->OpcodeSize++;
}
break;
}
}
break;
// POP DWORD PTR[REG/MEM/DISP]
case 0x8F:
{
wsprintf(menemonic,"%s ?? 快捷鍵說明
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