#define DDADR13		__REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */#define DSADR13		__REG(0x400002d4)  /* DMA Source Address Register Channel 13 */#define DTADR13		__REG(0x400002d8)  /* DMA Target Address Register Channel 13 */#define DCMD13		__REG(0x400002dc)  /* DMA Command Address Register Channel 13 */#define DDADR14		__REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */#define DSADR14		__REG(0x400002e4)  /* DMA Source Address Register Channel 14 */#define DTADR14		__REG(0x400002e8)  /* DMA Target Address Register Channel 14 */#define DCMD14		__REG(0x400002ec)  /* DMA Command Address Register Channel 14 */#define DDADR15		__REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */#define DSADR15		__REG(0x400002f4)  /* DMA Source Address Register Channel 15 */#define DTADR15		__REG(0x400002f8)  /* DMA Target Address Register Channel 15 */#define DCMD15		__REG(0x400002fc)  /* DMA Command Address Register Channel 15 */#define DDADR(x)	__REG2(0x40000200, (x) << 4)#define DSADR(x)	__REG2(0x40000204, (x) << 4)#define DTADR(x)	__REG2(0x40000208, (x) << 4)#define DCMD(x)		__REG2(0x4000020c, (x) << 4)#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */#define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */#define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */#define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) *//* default combinations */#define DCMD_RXPCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)#define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)#define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)/* * UARTs *//* Full Function UART (FFUART) */#define FFUART		FFRBR#define FFRBR		__REG(0x40100000)  /* Receive Buffer Register (read only) */#define FFTHR		__REG(0x40100000)  /* Transmit Holding Register (write only) */#define FFIER		__REG(0x40100004)  /* Interrupt Enable Register (read/write) */#define FFIIR		__REG(0x40100008)  /* Interrupt ID Register (read only) */#define FFFCR		__REG(0x40100008)  /* FIFO Control Register (write only) */#define FFLCR		__REG(0x4010000C)  /* Line Control Register (read/write) */#define FFMCR		__REG(0x40100010)  /* Modem Control Register (read/write) */#define FFLSR		__REG(0x40100014)  /* Line Status Register (read only) */#define FFMSR		__REG(0x40100018)  /* Modem Status Register (read only) */#define FFSPR		__REG(0x4010001C)  /* Scratch Pad Register (read/write) */#define FFISR		__REG(0x40100020)  /* Infrared Selection Register (read/write) */#define FFDLL		__REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */#define FFDLH		__REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) *//* Bluetooth UART (BTUART) */#define BTUART		BTRBR#define BTRBR		__REG(0x40200000)  /* Receive Buffer Register (read only) */#define BTTHR		__REG(0x40200000)  /* Transmit Holding Register (write only) */#define BTIER		__REG(0x40200004)  /* Interrupt Enable Register (read/write) */#define BTIIR		__REG(0x40200008)  /* Interrupt ID Register (read only) */#define BTFCR		__REG(0x40200008)  /* FIFO Control Register (write only) */#define BTLCR		__REG(0x4020000C)  /* Line Control Register (read/write) */#define BTMCR		__REG(0x40200010)  /* Modem Control Register (read/write) */#define BTLSR		__REG(0x40200014)  /* Line Status Register (read only) */#define BTMSR		__REG(0x40200018)  /* Modem Status Register (read only) */#define BTSPR		__REG(0x4020001C)  /* Scratch Pad Register (read/write) */#define BTISR		__REG(0x40200020)  /* Infrared Selection Register (read/write) */#define BTDLL		__REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */#define BTDLH		__REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) *//* Standard UART (STUART) */#define STUART		STRBR#define STRBR		__REG(0x40700000)  /* Receive Buffer Register (read only) */#define STTHR		__REG(0x40700000)  /* Transmit Holding Register (write only) */#define STIER		__REG(0x40700004)  /* Interrupt Enable Register (read/write) */#define STIIR		__REG(0x40700008)  /* Interrupt ID Register (read only) */#define STFCR		__REG(0x40700008)  /* FIFO Control Register (write only) */#define STLCR		__REG(0x4070000C)  /* Line Control Register (read/write) */#define STMCR		__REG(0x40700010)  /* Modem Control Register (read/write) */#define STLSR		__REG(0x40700014)  /* Line Status Register (read only) */#define STMSR		__REG(0x40700018)  /* Reserved */#define STSPR		__REG(0x4070001C)  /* Scratch Pad Register (read/write) */#define STISR		__REG(0x40700020)  /* Infrared Selection Register (read/write) */#define STDLL		__REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */#define STDLH		__REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */#define IER_UUE		(1 << 6)	/* UART Unit Enable */#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */#define IIR_TOD		(1 << 3)	/* Time Out Detected */#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */#define FCR_ITL_1	(0)#define FCR_ITL_8	(FCR_ITL1)#define FCR_ITL_16	(FCR_ITL2)#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */#define LCR_SB		(1 << 6)	/* Set Break */#define LCR_STKYP	(1 << 5)	/* Sticky Parity */#define LCR_EPS		(1 << 4)	/* Even Parity Select */#define LCR_PEN		(1 << 3)	/* Parity Enable */#define LCR_STB		(1 << 2)	/* Stop Bit */#define LCR_WLS1	(1 << 1)	/* Word Length Select */#define LCR_WLS0	(1 << 0)	/* Word Length Select */#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */#define LSR_BI		(1 << 4)	/* Break Interrupt */#define LSR_FE		(1 << 3)	/* Framing Error */#define LSR_PE		(1 << 2)	/* Parity Error */#define LSR_OE		(1 << 1)	/* Overrun Error */#define LSR_DR		(1 << 0)	/* Data Ready */#define MCR_LOOP	(1 << 4)	*/#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */#define MCR_RTS		(1 << 1)	/* Request to Send */#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */#define MSR_RI		(1 << 6)	/* Ring Indicator */#define MSR_DSR		(1 << 5)	/* Data Set Ready */#define MSR_CTS		(1 << 4)	/* Clear To Send */#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send *//* * IrSR (Infrared Selection Register) */#define IrSR_OFFSET 0x20#define IrSR_RXPL_NEG_IS_ZERO (1<<4)#define IrSR_RXPL_POS_IS_ZERO 0x0#define IrSR_TXPL_NEG_IS_ZERO (1<<3)#define IrSR_TXPL_POS_IS_ZERO 0x0#define IrSR_XMODE_PULSE_1_6  (1<<2)#define IrSR_XMODE_PULSE_3_16 0x0#define IrSR_RCVEIR_IR_MODE   (1<<1)#define IrSR_RCVEIR_UART_MODE 0x0#define IrSR_XMITIR_IR_MODE   (1<<0)#define IrSR_XMITIR_UART_MODE 0x0#define IrSR_IR_RECEIVE_ON (\		IrSR_RXPL_NEG_IS_ZERO | \		IrSR_TXPL_POS_IS_ZERO | \		IrSR_XMODE_PULSE_3_16 | \		IrSR_RCVEIR_IR_MODE   | \		IrSR_XMITIR_UART_MODE)#define IrSR_IR_TRANSMIT_ON (\		IrSR_RXPL_NEG_IS_ZERO | \		IrSR_TXPL_POS_IS_ZERO | \		IrSR_XMODE_PULSE_3_16 | \		IrSR_RCVEIR_UART_MODE | \		IrSR_XMITIR_IR_MODE)/* * I2C registers */#define IBMR		__REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */#define IDBR		__REG(0x40301688)  /* I2C Data Buffer Register - IDBR */#define ICR		__REG(0x40301690)  /* I2C Control Register - ICR */#define ISR		__REG(0x40301698)  /* I2C Status Register - ISR */#define ISAR		__REG(0x403016A0)  /* I2C Slave Address Register - ISAR */#define PWRIBMR		__REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */#define PWRIDBR		__REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */#define PWRICR		__REG(0x40f00190)  /* Power I2C Control Register - ICR */#define PWRISR		__REG(0x40f00198)  /* Power I2C Status Register - ISR */#define PWRISAR		__REG(0x40f001A0)  /* Power I2C Slave Address Register-ISAR *//* ----- Control register bits ---------------------------------------- */#define ICR_START	0x1		/* start bit */#define ICR_STOP	0x2		/* stop bit */#define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */#define ICR_TB		0x8		/* transfer byte bit */#define ICR_MA		0x10		/* master abort */#define ICR_SCLE	0x20		/* master clock enable, mona SCLEA */#define ICR_IUE		0x40		/* unit enable */#define ICR_GCD		0x80		/* general call disable */#define ICR_ITEIE	0x100		/* enable tx interrupts */#define ICR_IRFIE	0x200		/* enable rx interrupts, mona: DRFIE */#define ICR_BEIE	0x400		/* enable bus error ints */#define ICR_SSDIE	0x800		/* slave STOP detected int enable */#define ICR_ALDIE	0x1000		/* enable arbitration interrupt */#define ICR_SADIE	0x2000		/* slave address detected int enable */#define ICR_UR		0x4000		/* unit reset */#define ICR_FM		0x8000		/* Fast Mode *//* ----- Status register bits ----------------------------------------- */#define ISR_RWM		0x1		/* read/write mode */#define ISR_ACKNAK	0x2		/* ack/nak status */#define ISR_UB		0x4		/* unit busy */#define ISR_IBB		0x8		/* bus busy */#define ISR_SSD		0x10		/* slave stop detected */#define ISR_ALD		0x20		/* arbitration loss detected */#define ISR_ITE		0x40		/* tx buffer empty */#define ISR_IRF		0x80		/* rx buffer full */#define ISR_GCAD	0x100		/* general call address detected */#define ISR_SAD		0x200		/* slave address detected */#define ISR_BED		0x400		/* bus error no ACK/NAK *//* * Serial Audio Controller *//* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these * short defines because there is too much chance of namespace collision *//*#define SACR0		__REG(0x40400000)  /  Global Control Register *//*#define SACR1		__REG(0x40400004)  /  Serial Audio I 2 S/MSB-Justified Control Register *//*#define SASR0		__REG(0x4040000C)  /  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register *//*#define SAIMR		__REG(0x40400014)  /  Serial Audio Interrupt Mask Register *//*#define SAICR		__REG(0x40400018)  /  Serial Audio Interrupt Clear Register *//*#define SADIV		__REG(0x40400060)  /  Audio Clock Divider Register. *//*#define SADR		__REG(0x40400080)  /  Serial Audio Data Register (TX and RX FIFO access Register). *//* * AC97 Controller registers */#define POCR		__REG(0x40500000)  /* PCM Out Control Register */#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */#define PICR		__REG(0x40500004)  /* PCM In Control Register */#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */#define MCCR		__REG(0x40500008)  /* Mic In Control Register */#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */#define GCR		__REG(0x4050000C)  /* Global Control Register */#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */#define POSR		__REG(0x40500010)  /* PCM Out Status Register */#define POSR_FIFOE	(1 << 4)	/* FIFO error */#define PISR		__REG(0x40500014)  /* PCM In Status Register */#define PISR_FIFOE	(1 << 4)	/* FIFO error */