/* * (C) Copyright 2003 * Ingo Assmus <ingo.assmus@keymile.com> * * based on - Driver for MV64460X ethernet ports * Copyright (C) 2002 rabeeh@galileo.co.il * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//********************************************************************************* gt64460r.h - GT-64460 Internal registers definition file.** DESCRIPTION:*	None.** DEPENDENCIES:*	None.********************************************************************************/#ifndef __INCmv_regsh#define __INCmv_regsh#define MV64460/* Supported by the Atlantis */#define MV64460_INCLUDE_PCI_1#define MV64460_INCLUDE_PCI_0_ARBITER#define MV64460_INCLUDE_PCI_1_ARBITER#define MV64460_INCLUDE_SNOOP_SUPPORT#define MV64460_INCLUDE_P2P#define MV64460_INCLUDE_ETH_PORT_2#define MV64460_INCLUDE_CPU_MAPPING#define MV64460_INCLUDE_MPSC/* Not supported features */#undef	INCLUDE_CNTMR_4_7#undef	INCLUDE_DMA_4_7/****************************************//* Processor Address Space		*//****************************************//* DDR SDRAM BAR and size registers */#define MV64460_CS_0_BASE_ADDR					    0x008#define MV64460_CS_0_SIZE					    0x010#define MV64460_CS_1_BASE_ADDR					    0x208#define MV64460_CS_1_SIZE					    0x210#define MV64460_CS_2_BASE_ADDR					    0x018#define MV64460_CS_2_SIZE					    0x020#define MV64460_CS_3_BASE_ADDR					    0x218#define MV64460_CS_3_SIZE					    0x220/* Devices BAR and size registers */#define MV64460_DEV_CS0_BASE_ADDR				    0x028#define MV64460_DEV_CS0_SIZE					    0x030#define MV64460_DEV_CS1_BASE_ADDR				    0x228#define MV64460_DEV_CS1_SIZE					    0x230#define MV64460_DEV_CS2_BASE_ADDR				    0x248#define MV64460_DEV_CS2_SIZE					    0x250#define MV64460_DEV_CS3_BASE_ADDR				    0x038#define MV64460_DEV_CS3_SIZE					    0x040#define MV64460_BOOTCS_BASE_ADDR				    0x238#define MV64460_BOOTCS_SIZE					    0x240/* PCI 0 BAR and size registers */#define MV64460_PCI_0_IO_BASE_ADDR				    0x048#define MV64460_PCI_0_IO_SIZE					    0x050#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058#define MV64460_PCI_0_MEMORY0_SIZE				    0x060#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080#define MV64460_PCI_0_MEMORY1_SIZE				    0x088#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258#define MV64460_PCI_0_MEMORY2_SIZE				    0x260#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280#define MV64460_PCI_0_MEMORY3_SIZE				    0x288/* PCI 1 BAR and size registers */#define MV64460_PCI_1_IO_BASE_ADDR				    0x090#define MV64460_PCI_1_IO_SIZE					    0x098#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8/* SRAM base address */#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268/* internal registers space base address */#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068/* Enables the CS , DEV_CS , PCI 0 and PCI 1   windows above */#define MV64460_BASE_ADDR_ENABLE				    0x278/****************************************//* PCI remap registers			*//****************************************/      /* PCI 0 */#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338      /* PCI 1 */#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8/****************************************//*	   CPU Control Registers	*//****************************************/#define MV64460_CPU_CONFIG					    0x000#define MV64460_CPU_MODE					    0x120#define MV64460_CPU_MASTER_CONTROL				    0x160#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168/****************************************//* SMP RegisterS			*//****************************************/#define MV64460_SMP_WHO_AM_I					    0x200#define MV64460_SMP_CPU0_DOORBELL				    0x214#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C#define MV64460_SMP_CPU1_DOORBELL				    0x224#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C#define MV64460_SMP_SEMAPHOR0					    0x244#define MV64460_SMP_SEMAPHOR1					    0x24c#define MV64460_SMP_SEMAPHOR2					    0x254#define MV64460_SMP_SEMAPHOR3					    0x25c#define MV64460_SMP_SEMAPHOR4					    0x264#define MV64460_SMP_SEMAPHOR5					    0x26c#define MV64460_SMP_SEMAPHOR6					    0x274#define MV64460_SMP_SEMAPHOR7					    0x27c/****************************************//*  CPU Sync Barrier Register		*//****************************************/#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8/****************************************//* CPU Access Protect			*//****************************************/#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8/****************************************//*	    CPU Error Report		*//****************************************/#define MV64460_CPU_ERROR_ADDR_LOW				    0x070#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078#define MV64460_CPU_ERROR_DATA_LOW				    0x128#define MV64460_CPU_ERROR_DATA_HIGH				    0x130#define MV64460_CPU_ERROR_PARITY				    0x138#define MV64460_CPU_ERROR_CAUSE					    0x140#define MV64460_CPU_ERROR_MASK					    0x148/****************************************//*	CPU Interface Debug Registers	*//****************************************/#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378#define MV64460_PUNIT_MMASK					    0x3e4/****************************************//*  Integrated SRAM Registers		*//****************************************/#define MV64460_SRAM_CONFIG					    0x380#define MV64460_SRAM_TEST_MODE					    0X3F4#define MV64460_SRAM_ERROR_CAUSE				    0x388#define MV64460_SRAM_ERROR_ADDR					    0x390#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8#define MV64460_SRAM_ERROR_DATA_LOW				    0x398#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8/****************************************//* SDRAM Configuration			*//****************************************/#define MV64460_SDRAM_CONFIG					    0x1400#define MV64460_D_UNIT_CONTROL_LOW				    0x1404#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c#define MV64460_SDRAM_ADDR_CONTROL				    0x1410#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414#define MV64460_SDRAM_OPERATION					    0x1418#define MV64460_SDRAM_MODE					    0x141c#define MV64460_EXTENDED_DRAM_MODE				    0x1420#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4/****************************************//* SDRAM Error Report			*//****************************************/#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440#define MV64460_SDRAM_ERROR_ADDR				    0x1450#define MV64460_SDRAM_RECEIVED_ECC				    0x1448#define MV64460_SDRAM_CALCULATED_ECC				    0x144c#define MV64460_SDRAM_ECC_CONTROL				    0x1454#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458/******************************************//*  Controlled Delay Line (CDL) Registers *//******************************************/#define MV64460_DFCDL_CONFIG0					    0x1480#define MV64460_DFCDL_CONFIG1					    0x1484#define MV64460_DLL_WRITE					    0x1488#define MV64460_DLL_READ					    0x148c#define MV64460_SRAM_ADDR					    0x1490