#define MV64460_SRAM_DATA0					    0x1494#define MV64460_SRAM_DATA1					    0x1498#define MV64460_SRAM_DATA2					    0x149c#define MV64460_DFCL_PROBE					    0x14a0/******************************************//*   Debug Registers			  *//******************************************/#define MV64460_DUNIT_DEBUG_LOW					    0x1460#define MV64460_DUNIT_DEBUG_HIGH				    0x1464#define MV64460_DUNIT_MMASK					    0X1b40/****************************************//* Device Parameters			*//****************************************/#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4/****************************************//* Device interrupt registers		*//****************************************/#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4#define MV64460_DEVICE_ERROR_ADDR				    0x4d8#define MV64460_DEVICE_ERROR_DATA				    0x4dc#define MV64460_DEVICE_ERROR_PARITY				    0x4e0/****************************************//* Device debug registers		*//****************************************/#define MV64460_DEVICE_DEBUG_LOW				    0x4e4#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8#define MV64460_RUNIT_MMASK					    0x4f0/****************************************//* PCI Slave Address Decoding registers *//****************************************/#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8/***********************************//*   PCI Control Register Map	   *//***********************************/#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C#define MV64460_PCI_0_COMMAND					    0xc00#define MV64460_PCI_1_COMMAND					    0xc80#define MV64460_PCI_0_MODE					    0xd00#define MV64460_PCI_1_MODE					    0xd80#define MV64460_PCI_0_RETRY					    0xc04#define MV64460_PCI_1_RETRY					    0xc84#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90#define MV64460_PCI_0_P2P_CONFIG				    0x1d14#define MV64460_PCI_1_P2P_CONFIG				    0x1d94#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8/****************************************//*   PCI Configuration Access Registers *//****************************************/#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc#define MV64460_PCI_1_CONFIG_ADDR				    0xc78#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4/****************************************//*   PCI Error Report Registers		*//****************************************/#define MV64460_PCI_0_SERR_MASK					    0xc28#define MV64460_PCI_1_SERR_MASK					    0xca8#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8#define MV64460_PCI_0_ERROR_MASK				    0x1d5c#define MV64460_PCI_1_ERROR_MASK				    0x1ddc/****************************************//*   PCI Debug Registers		*//****************************************/#define MV64460_PCI_0_MMASK					    0X1D24#define MV64460_PCI_1_MMASK					    0X1DA4/*********************************************//* PCI Configuration, Function 0, Registers  *//*********************************************/#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000#define MV64460_PCI_STATUS_AND_COMMAND				    0x004#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C       /* capability list */#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044#define MV64460_PCI_VPD_ADDR					    0x048#define MV64460_PCI_VPD_DATA					    0x04c#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c#define MV64460_PCI_X_COMMAND					    0x060#define MV64460_PCI_X_STATUS					    0x064#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068/***********************************************//*   PCI Configuration, Function 1, Registers  *//***********************************************/#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c