Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Wed Mar 18 22:17:21 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off top -c top
Info: Selected device EP1C6Q240C8 for design "top"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 121 of 121 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Warning: No exact pin location assignment(s) for 54 pins of 54 total pins
    Info: Pin dataout[7] not assigned to an exact location on the device
    Info: Pin dataout[6] not assigned to an exact location on the device
    Info: Pin dataout[5] not assigned to an exact location on the device
    Info: Pin dataout[4] not assigned to an exact location on the device
    Info: Pin dataout[3] not assigned to an exact location on the device
    Info: Pin dataout[2] not assigned to an exact location on the device
    Info: Pin dataout[1] not assigned to an exact location on the device
    Info: Pin dataout[0] not assigned to an exact location on the device
    Info: Pin dataram[7] not assigned to an exact location on the device
    Info: Pin dataram[6] not assigned to an exact location on the device
    Info: Pin dataram[5] not assigned to an exact location on the device
    Info: Pin dataram[4] not assigned to an exact location on the device
    Info: Pin dataram[3] not assigned to an exact location on the device
    Info: Pin dataram[2] not assigned to an exact location on the device
    Info: Pin dataram[1] not assigned to an exact location on the device
    Info: Pin dataram[0] not assigned to an exact location on the device
    Info: Pin full not assigned to an exact location on the device
    Info: Pin ready not assigned to an exact location on the device
    Info: Pin adclk not assigned to an exact location on the device
    Info: Pin wr_ram not assigned to an exact location on the device
    Info: Pin rd_ram not assigned to an exact location on the device
    Info: Pin clk_test not assigned to an exact location on the device
    Info: Pin addre[17] not assigned to an exact location on the device
    Info: Pin addre[16] not assigned to an exact location on the device
    Info: Pin addre[15] not assigned to an exact location on the device
    Info: Pin addre[14] not assigned to an exact location on the device
    Info: Pin addre[13] not assigned to an exact location on the device
    Info: Pin addre[12] not assigned to an exact location on the device
    Info: Pin addre[11] not assigned to an exact location on the device
    Info: Pin addre[10] not assigned to an exact location on the device
    Info: Pin addre[9] not assigned to an exact location on the device
    Info: Pin addre[8] not assigned to an exact location on the device
    Info: Pin addre[7] not assigned to an exact location on the device
    Info: Pin addre[6] not assigned to an exact location on the device
    Info: Pin addre[5] not assigned to an exact location on the device
    Info: Pin addre[4] not assigned to an exact location on the device
    Info: Pin addre[3] not assigned to an exact location on the device
    Info: Pin addre[2] not assigned to an exact location on the device
    Info: Pin addre[1] not assigned to an exact location on the device
    Info: Pin addre[0] not assigned to an exact location on the device
    Info: Pin st[1] not assigned to an exact location on the device
    Info: Pin st[0] not assigned to an exact location on the device
    Info: Pin clk_cpu not assigned to an exact location on the device
    Info: Pin rst not assigned to an exact location on the device
    Info: Pin clkin not assigned to an exact location on the device
    Info: Pin change not assigned to an exact location on the device
    Info: Pin datain[7] not assigned to an exact location on the device
    Info: Pin datain[6] not assigned to an exact location on the device
    Info: Pin datain[5] not assigned to an exact location on the device
    Info: Pin datain[4] not assigned to an exact location on the device
    Info: Pin datain[3] not assigned to an exact location on the device
    Info: Pin datain[2] not assigned to an exact location on the device
    Info: Pin datain[1] not assigned to an exact location on the device
    Info: Pin datain[0] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clkin" to use Global clock in PIN 29
Info: Automatically promoted some destinations of signal "clk_select:inst2|clk~16" to use Global clock
    Info: Destination "clk_test" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "com:inst|current_state.s3" to use Global clock
    Info: Destination "dataout[3]" may be non-global or may not use global clock
    Info: Destination "dataout[2]" may be non-global or may not use global clock
    Info: Destination "dataout[1]" may be non-global or may not use global clock
    Info: Destination "dataout[0]" may be non-global or may not use global clock
    Info: Destination "dataout[4]" may be non-global or may not use global clock
    Info: Destination "dataout[5]" may be non-global or may not use global clock
    Info: Destination "dataout[6]" may be non-global or may not use global clock
    Info: Destination "dataout[7]" may be non-global or may not use global clock
    Info: Destination "com:inst|current_state.s3" may be non-global or may not use global clock
    Info: Destination "com:inst|adclk~6" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Automatically promoted signal "rst" to use Global clock in PIN 28
Info: Automatically promoted some destinations of signal "com:inst|flag~0" to use Global clock
    Info: Destination "com:inst|comb_181" may be non-global or may not use global clock
    Info: Destination "st[0]" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 52 (unused VREF, 3.30 VCCIO, 10 input, 34 output, 8 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  40 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.593 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y14; Fanout = 5; REG Node = 'addre:inst1|count[4]'
    Info: 2: + IC(1.141 ns) + CELL(0.575 ns) = 1.716 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'addre:inst1|Add0~294COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.796 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'addre:inst1|Add0~292COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 2.404 ns; Loc. = LAB_X9_Y15; Fanout = 1; COMB Node = 'addre:inst1|Add0~289'
    Info: 5: + IC(0.745 ns) + CELL(0.590 ns) = 3.739 ns; Loc. = LAB_X8_Y14; Fanout = 1; COMB Node = 'addre:inst1|count~200'
    Info: 6: + IC(0.116 ns) + CELL(0.738 ns) = 4.593 ns; Loc. = LAB_X8_Y14; Fanout = 5; REG Node = 'addre:inst1|count[6]'
    Info: Total cell delay = 2.591 ns ( 56.41 % )
    Info: Total interconnect delay = 2.002 ns ( 43.59 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X0_Y11 to location X11_Y21
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: com:inst|comb_181
        Info: Type bidirectional pin dataram[7] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[6] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[5] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[4] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[3] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[2] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[1] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin dataram[0] uses the 3.3-V LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 167 megabytes of memory during processing
    Info: Processing ended: Wed Mar 18 22:17:25 2009
    Info: Elapsed time: 00:00:04