?? moxa.c
字號:
//
// MOXA.C
//
#include "Moxa.h"
#define RBR 0
#define THR 0
#define IER 1
#define IIR 2
#define FCR 2
#define LCR 3
#define MCR 4
#define LSR 5
#define MSR 6
#define SCR 7
#define DLL 0
#define DLM 1
#define PORT_BASE_UART_ADDRESS(x) (UCHAR*)0xE880+(x-1)*8
UCHAR Port1Value,Port2Value;
UCHAR WriteBuffer[2][1024];
UCHAR ReadBuffer[2][32];
int Writecounter[2];
int Readcounter[2];
static BOOL WriteFlag[2];
void
DisableInterruptsOnChip ( )
{
_asm cli;
}
//
// EnableInterruptsOnChip: Enable Interrupts on Chip once you have
// attach to the interrupt vector
//
void
EnableInterruptsOnChip ( )
{
_asm sti;
}
void
MsgAndExit (
char *msg //input: message to print to screen
)
{
RtPrintf ( "Error: %s (0x%X)\n", msg, RtGetLastError ( ) );
RtExitProcess ( 1 );
}
BOOLEAN
RTAPI
DeviceIST (
PVOID pContext
)
{
BOOLEAN bHandled = TRUE;
//int counter =0;
UCHAR temp1,temp2;
temp1=RtReadPortUchar(PORT_BASE_UART_ADDRESS(1)+IIR);
temp2=RtReadPortUchar(PORT_BASE_UART_ADDRESS(2)+IIR);
while (((temp1&0X01)==0)||((temp2&0X01)==0))
{
switch(temp1&0X0F) {
case 0X02:
if (WriteFlag[0] == TRUE)
{
if (WriteBuffer[0][Writecounter[0]]!='\0')
{
RtWritePortUchar(PORT_BASE_UART_ADDRESS(1)+THR,WriteBuffer[0][Writecounter[0]++]);
//RtPrintf("1---Interrupt!\n");
}
else
WriteFlag[0] = FALSE;
}
break;
case 0X04:
ReadBuffer[0][Readcounter[0]++] = RtReadPortUchar(PORT_BASE_UART_ADDRESS(1)+RBR);
if (Readcounter[0]==32)
{
Readcounter[0] = 0;
}
break;
default:
//RtPrintf("1---Interrupt!\n");
break;
}
switch(temp2&0X0F) {
case 0X02:
if (WriteFlag[1] == TRUE)
{
if (WriteBuffer[1][Writecounter[1]]!='\0')
{
RtWritePortUchar(PORT_BASE_UART_ADDRESS(2)+THR,WriteBuffer[1][Writecounter[1]++]);
//RtPrintf("1---Interrupt!\n");
}
else
WriteFlag[1] = FALSE;
}
break;
case 0X04:
ReadBuffer[1][Readcounter[1]++] = RtReadPortUchar(PORT_BASE_UART_ADDRESS(2)+RBR);
if (Readcounter[1]==32)
{
Readcounter[1] = 0;
}
break;
default:
//RtPrintf("2---Interrupt!\n");
break;
}
temp1=RtReadPortUchar(PORT_BASE_UART_ADDRESS(1)+IIR);
temp2=RtReadPortUchar(PORT_BASE_UART_ADDRESS(2)+IIR);
}
return bHandled;
}
BOOL WriteMoxaPort(int port, UCHAR Buffer[])
{
int counter=0;
WriteFlag[port-1] = TRUE;
while (Buffer[counter]!='\0')
{
WriteBuffer[port-1][counter]=Buffer[counter];
counter++;
}
WriteBuffer[port-1][counter]=Buffer[counter];
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+THR,WriteBuffer[port-1][Writecounter[port-1]++]);
return TRUE;
}
BOOL ReadMoxaPort(int port, UCHAR Buffer[], int ReadByOffset)
{
static int m = 0;
int counter=0;
for (counter=0;counter<ReadByOffset;counter++)
{
Buffer[counter]=ReadBuffer[port-1][m++];
if (m==32)
{
m=0;
}
}
Buffer[counter]='\0';
return TRUE;
}
BOOL OpenInterruptMode(ULONG BusNumber,PCI_SLOT_NUMBER *pSlotNumber,PPCI_COMMON_CONFIG PciData)
{
//the variables for interrupt mode(required)
HANDLE intHandler; // interrupt handler
ULONG irqLevel; // interrupt level
ULONG irqVector; // interrupt IRQ
RtWritePortUchar(PORT_BASE_UART_ADDRESS(1)+IER,0x03);
RtWritePortUchar(PORT_BASE_UART_ADDRESS(2)+IER,0x03);
irqLevel = PciData->u.type0.InterruptLine;
irqVector = irqLevel;
//
// Disable interrupts on the chip
//
DisableInterruptsOnChip ( );
//
// Attempt to attach to the interrupt
//
intHandler = RtAttachInterruptVector (
NULL, // security attributes (default)
0, // stack size (default)
DeviceIST, // pointer to Interrupt Service Thread (IST).
NULL, // context argument
RT_PRIORITY_MAX, // thread priority for the handler routine
PCIBus, // interface type
BusNumber, // bus number
irqLevel, // interrupt level
irqVector // interrupt vector
);
if( intHandler == NULL )
{
MsgAndExit( "Could not attach to the interrupt for this device." );
}
//
// Re-enable interrupts on the chip
//
EnableInterruptsOnChip ( );
return TRUE;
}
//
// DeviceSearch: Searches for the first instance of a
// given card on the machine 's PCI buses. It returns the
// bus number when the specified card has been found,
// or returns -1 if no device found.
//
int
DeviceSearch (
int vendorID, // input: card Vendor ID
int deviceID, // input: card Device ID
PCI_SLOT_NUMBER *pSlotNumber, // output: pointer to slot number
PPCI_COMMON_CONFIG PciData // output: PCI card information
)
{
ULONG bus; // bus number
ULONG deviceNumber; // logical slot number for the PCI adapter
ULONG functionNumber; // function number on the specified adapter
ULONG bytesWritten; // return value from RtGetBusDataByOffset
BOOLEAN bFlag = TRUE;
pSlotNumber->u.bits.Reserved = 0;
// All PCI cards have been searched when we are out of PCI busses. (bFlag = FALSE)
for ( bus=0; bFlag; bus++ )
{
for ( deviceNumber=0; deviceNumber < PCI_MAX_DEVICES && bFlag; deviceNumber++ )
{
pSlotNumber->u.bits.DeviceNumber = deviceNumber;
for ( functionNumber=0; functionNumber < PCI_MAX_FUNCTION; functionNumber++ )
{
pSlotNumber->u.bits.FunctionNumber = functionNumber;
bytesWritten = RtGetBusDataByOffset (
PCIConfiguration, // type of bus data to be retrieved
bus, // zero-based number of the bus
pSlotNumber->u.AsULONG, // logical slot number
PciData, // pointer to a buffer for configuration information
0, // byte offset into buffer
PCI_COMMON_HDR_LENGTH // length of buffer
);
if ( bytesWritten == 0 )
{
// out of PCI buses done
bFlag = FALSE;
break;
}
if ( bytesWritten == 2 && PciData->VendorID == PCI_INVALID_VENDORID )
{
// no device at this slot number, skip to next slot
break;
}
//
// If device is found return, otherwise continue
// until all buses have been searched.
// Base Class and sub Class can also be used to find your
// specific device.
//
if ( ( PciData->VendorID == vendorID ) && ( PciData->DeviceID == deviceID ) )
return bus;
} // functionNumber loop
} // deviceNumber loop
} // bus loop
return -1;
}
void DeviceInfo(ULONG busNumber,PCI_SLOT_NUMBER slotNumber,PPCI_COMMON_CONFIG pciData)
{
int counter;
RtPrintf("busNumber = %d\n\n",busNumber);
RtPrintf("slotNumber.u.AsULONG = %d\n",slotNumber.u.AsULONG);
RtPrintf("slotNumber.u.bits.DeviceNumber = %d\n",slotNumber.u.bits.DeviceNumber);
RtPrintf("slotNumber.u.bits.FunctionNumber = %d\n",slotNumber.u.bits.FunctionNumber);
RtPrintf("slotNumber.u.bits.Reserved = %d\n\n",slotNumber.u.bits.Reserved);
RtPrintf("pciData->VendorID = 0X%x\n",pciData->VendorID);
RtPrintf("pciData->DeviceID = 0X%x\n",pciData->DeviceID);
RtPrintf("pciData->Command = 0X%x\n",pciData->Command);
RtPrintf("pciData->Status = 0X%x\n",pciData->Status);
RtPrintf("pciData->RevisionID = 0X%x\n",pciData->RevisionID);
RtPrintf("pciData->ProgIf = 0X%x\n",pciData->ProgIf);
RtPrintf("pciData->SubClass = 0X%x\n",pciData->SubClass);
RtPrintf("pciData->BaseClass = 0X%x\n",pciData->BaseClass);
RtPrintf("pciData->CacheLineSize = 0X%x\n",pciData->CacheLineSize);
RtPrintf("pciData->LatencyTimer = 0X%x\n",pciData->LatencyTimer);
RtPrintf("pciData->HeaderType = 0X%x\n",pciData->HeaderType);
RtPrintf("pciData->BIST = 0X%x\n",pciData->BIST);
for (counter=0;counter<PCI_TYPE0_ADDRESSES;counter++)
RtPrintf("pciData->u.type0.BaseAddresses[%d] = 0X%x\n",counter,pciData->u.type0.BaseAddresses[counter]);
RtPrintf("pciData->u.type0.CIS = 0X%x\n",pciData->u.type0.CIS);
RtPrintf("pciData->u.type0.SubVendorID = 0X%x\n",pciData->u.type0.SubVendorID);
RtPrintf("pciData->u.type0.SubSystemID = 0X%x\n",pciData->u.type0.SubSystemID);
RtPrintf("pciData->u.type0.ROMBaseAddress = 0X%x\n",pciData->u.type0.ROMBaseAddress);
RtPrintf("pciData->u.type0.InterruptLine = %d\n",pciData->u.type0.InterruptLine);
RtPrintf("pciData->u.type0.InterruptPin = %d\n",pciData->u.type0.InterruptPin);
RtPrintf("pciData->u.type0.MinimumGrant = %d\n",pciData->u.type0.MinimumGrant);
RtPrintf("pciData->u.type0.MaximumLatency = %d\n",pciData->u.type0.MaximumLatency);
return;
}
BOOL PutChar(int port, UCHAR c)
{
UCHAR temp;
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+LSR);
if (temp&0X20)
{
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+THR,c);
return TRUE;
}
return FALSE;
}
UCHAR GetChar(int port)
{
UCHAR temp;
do {
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+LSR);
} while((temp&0X01)==0);
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+MSR);
//RtPrintf("MSR %d = %x\n",port,temp);
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+LSR);
//RtPrintf("LSR %d = %x\n",port,temp);
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+RBR);
//RtPrintf("RBR %d = %x\n",port,temp);
return temp;
}
void PortStatus(int port)
{
UCHAR temp;
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+MSR);
RtPrintf("MSR %d = %x\n",port,temp);
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+LSR);
RtPrintf("LSR %d = %x\n",port,temp);
temp = RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+RBR);
RtPrintf("RBR %d = %x\n",port,temp);
}
BOOL OpenMoxaPort(int port, int BandRate, int WordLength, int parity)
{
int divisor=(int)(115200L/BandRate);
UCHAR c;
int setting;
int init=0;
for(init=0;init<1024;init++)
WriteBuffer[port-1][init]='\0';
for(init=0;init<32;init++)
ReadBuffer[port-1][32]='\0';
Writecounter[port-1] =0;
Readcounter[port-1] =0;
WriteFlag[port-1] = TRUE;
//set the band rate
c=RtReadPortUchar(PORT_BASE_UART_ADDRESS(port)+LCR);
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+LCR,(UCHAR)(c|0x80));
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+DLL,(UCHAR)(divisor&0X00FF));
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+DLM,(UCHAR)((divisor>>8)&0X00FF));
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+LCR,(UCHAR)(c));
//set the word length, the stop bit and parity
setting=WordLength-5;
setting|=0X04;
if(parity == 0)
{
setting |=0X00;
}
if(parity == 1)
{
setting |=0X08;
}
if(parity == 2)
{
setting |=0X18;
}
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+LCR,(UCHAR)setting);
//enable autoflow control
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+MCR,0x00);
//set the FIFO
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+FCR,0x07);
return TRUE;
}
BOOL OpenPolledMode (int port)
{
RtWritePortUchar(PORT_BASE_UART_ADDRESS(port)+IER,0x00);
return TRUE;
}
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