{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 08 14:30:26 2008 " "Info: Processing started: Sat Nov 08 14:30:26 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VGA_Controller -c VGA_Controller " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA_Controller -c VGA_Controller" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA_Controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VGA_Controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VGA_Controller-behave " "Info: Found design unit 1: VGA_Controller-behave" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 23 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 VGA_Controller " "Info: Found entity 1: VGA_Controller" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VGA_Controller " "Info: Elaborating entity \"VGA_Controller\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[1\] bt\[0\] " "Info (13350): Duplicate register \"bt\[1\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[2\] bt\[0\] " "Info (13350): Duplicate register \"bt\[2\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[3\] bt\[0\] " "Info (13350): Duplicate register \"bt\[3\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[4\] bt\[0\] " "Info (13350): Duplicate register \"bt\[4\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[5\] bt\[0\] " "Info (13350): Duplicate register \"bt\[5\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[6\] bt\[0\] " "Info (13350): Duplicate register \"bt\[6\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[7\] bt\[0\] " "Info (13350): Duplicate register \"bt\[7\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[8\] bt\[0\] " "Info (13350): Duplicate register \"bt\[8\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bt\[9\] bt\[0\] " "Info (13350): Duplicate register \"bt\[9\]\" merged to single register \"bt\[0\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[0\] rt\[9\] " "Info (13350): Duplicate register \"rt\[0\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[1\] rt\[9\] " "Info (13350): Duplicate register \"rt\[1\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[2\] rt\[9\] " "Info (13350): Duplicate register \"rt\[2\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[3\] rt\[9\] " "Info (13350): Duplicate register \"rt\[3\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[4\] rt\[9\] " "Info (13350): Duplicate register \"rt\[4\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[5\] rt\[9\] " "Info (13350): Duplicate register \"rt\[5\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[6\] rt\[9\] " "Info (13350): Duplicate register \"rt\[6\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[7\] rt\[9\] " "Info (13350): Duplicate register \"rt\[7\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rt\[8\] rt\[9\] " "Info (13350): Duplicate register \"rt\[8\]\" merged to single register \"rt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[8\] gt\[9\] " "Info (13350): Duplicate register \"gt\[8\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[7\] gt\[9\] " "Info (13350): Duplicate register \"gt\[7\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[6\] gt\[9\] " "Info (13350): Duplicate register \"gt\[6\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[5\] gt\[9\] " "Info (13350): Duplicate register \"gt\[5\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[4\] gt\[9\] " "Info (13350): Duplicate register \"gt\[4\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[3\] gt\[9\] " "Info (13350): Duplicate register \"gt\[3\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[2\] gt\[9\] " "Info (13350): Duplicate register \"gt\[2\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[1\] gt\[9\] " "Info (13350): Duplicate register \"gt\[1\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gt\[0\] gt\[9\] " "Info (13350): Duplicate register \"gt\[0\]\" merged to single register \"gt\[9\]\"" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 142 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 28 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "BLANK VCC " "Warning (13410): Pin \"BLANK\" is stuck at VCC" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SYNC VCC " "Warning (13410): Pin \"SYNC\" is stuck at VCC" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "84 " "Info: Implemented 84 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Info: Implemented 35 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "47 " "Info: Implemented 47 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Peak virtual memory: 180 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 14:30:34 2008 " "Info: Processing ended: Sat Nov 08 14:30:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}