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-- and other software and tools, and its AMPP partner logic 
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--Y3L1 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~151
--operation mode is normal

Y3L1_carry_eqn = Y3L3;
Y3L1 = !Y3L1_carry_eqn;


--BB1_3 is sequence:103|74393b:25|3
--operation mode is normal

BB1_3_lut_out = !BB1_3;
BB1_3 = DFFEAS(BB1_3_lut_out, !CLK, G1_11, , BB1_1, , , , );


--BB1_9 is sequence:103|74393b:25|9
--operation mode is normal

BB1_9_lut_out = !BB1_9;
BB1_9 = DFFEAS(BB1_9_lut_out, !CLK, G1_11, , BB1_11, , , , );


--BB1_1 is sequence:103|74393b:25|1
--operation mode is normal

BB1_1_lut_out = !BB1_1;
BB1_1 = DFFEAS(BB1_1_lut_out, !CLK, G1_11, , , , , , );


--BB1_5 is sequence:103|74393b:25|5
--operation mode is normal

BB1_5_lut_out = !BB1_5;
BB1_5 = DFFEAS(BB1_5_lut_out, !CLK, G1_11, , BB1L4, , , , );


--J1L2 is sequence:103|33~19
--operation mode is normal

J1L2 = BB1_3 & BB1_9 & !BB1_1 & !BB1_5;


--J1_37 is sequence:103|37
--operation mode is normal

J1_37 = BB1_5 & !BB1_1 & !BB1_3 & !BB1_9;


--J1_35 is sequence:103|35
--operation mode is normal

J1_35 = BB1_5 & BB1_9 & !BB1_1 & !BB1_3;


--B4_12 is 74273b:21|12
--operation mode is normal

B4_12_lut_out = L1_q_a[23];
B4_12 = DFFEAS(B4_12_lut_out, 40, CLRN, , , , , , );


--B2_14 is 74273b:3|14
--operation mode is normal

B2_14_lut_out = L1_q_a[13];
B2_14 = DFFEAS(B2_14_lut_out, 40, CLRN, , , , , , );


--97 is 97
--operation mode is normal

97 = J1_35 & (B4_12 # B2_14) # !CLRN;


--J1L1 is sequence:103|31~19
--operation mode is normal

J1L1 = BB1_3 & BB1_5 & !BB1_1 & !BB1_9;


--B6_12 is 8cpu:92|74273b:7|12
--operation mode is normal

B6_12_lut_out = M3L81;
B6_12 = DFFEAS(B6_12_lut_out, H1_12, VCC, , , , , , );


--B6_13 is 8cpu:92|74273b:7|13
--operation mode is normal

B6_13_lut_out = M3L51;
B6_13 = DFFEAS(B6_13_lut_out, H1_12, VCC, , , , , , );


--B6_14 is 8cpu:92|74273b:7|14
--operation mode is normal

B6_14_lut_out = M3L11;
B6_14 = DFFEAS(B6_14_lut_out, H1_12, VCC, , , , , , );


--B6_15 is 8cpu:92|74273b:7|15
--operation mode is normal

B6_15_lut_out = M3L2;
B6_15 = DFFEAS(B6_15_lut_out, H1_12, VCC, , , , , , );


--B6_16 is 8cpu:92|74273b:7|16
--operation mode is normal

B6_16_lut_out = M2L71;
B6_16 = DFFEAS(B6_16_lut_out, H1_12, VCC, , , , , , );


--B6_17 is 8cpu:92|74273b:7|17
--operation mode is normal

B6_17_lut_out = M2L31;
B6_17 = DFFEAS(B6_17_lut_out, H1_12, VCC, , , , , , );


--B6_18 is 8cpu:92|74273b:7|18
--operation mode is normal

B6_18_lut_out = M2L9;
B6_18 = DFFEAS(B6_18_lut_out, H1_12, VCC, , , , , , );


--B6_19 is 8cpu:92|74273b:7|19
--operation mode is normal

B6_19_lut_out = M2L2;
B6_19 = DFFEAS(B6_19_lut_out, H1_12, VCC, , , , , , );


--B1_12 is 74273b:2|12
--operation mode is normal

B1_12_lut_out = L1_q_a[7];
B1_12 = DFFEAS(B1_12_lut_out, 40, CLRN, , , , , , );


--B1_13 is 74273b:2|13
--operation mode is normal

B1_13_lut_out = L1_q_a[6];
B1_13 = DFFEAS(B1_13_lut_out, 40, CLRN, , , , , , );


--B1_14 is 74273b:2|14
--operation mode is normal

B1_14_lut_out = L1_q_a[5];
B1_14 = DFFEAS(B1_14_lut_out, 40, CLRN, , , , , , );


--B1_15 is 74273b:2|15
--operation mode is normal

B1_15_lut_out = L1_q_a[4];
B1_15 = DFFEAS(B1_15_lut_out, 40, CLRN, , , , , , );


--B1_16 is 74273b:2|16
--operation mode is normal

B1_16_lut_out = L1_q_a[3];
B1_16 = DFFEAS(B1_16_lut_out, 40, CLRN, , , , , , );


--B1_17 is 74273b:2|17
--operation mode is normal

B1_17_lut_out = L1_q_a[2];
B1_17 = DFFEAS(B1_17_lut_out, 40, CLRN, , , , , , );


--B1_18 is 74273b:2|18
--operation mode is normal

B1_18_lut_out = L1_q_a[1];
B1_18 = DFFEAS(B1_18_lut_out, 40, CLRN, , , , , , );


--B1_19 is 74273b:2|19
--operation mode is normal

B1_19_lut_out = L1_q_a[0];
B1_19 = DFFEAS(B1_19_lut_out, 40, CLRN, , , , , , );


--B2_12 is 74273b:3|12
--operation mode is normal

B2_12_lut_out = L1_q_a[15];
B2_12 = DFFEAS(B2_12_lut_out, 40, CLRN, , , , , , );


--B2_13 is 74273b:3|13
--operation mode is normal

B2_13_lut_out = L1_q_a[14];
B2_13 = DFFEAS(B2_13_lut_out, 40, CLRN, , , , , , );


--B2_15 is 74273b:3|15
--operation mode is normal

B2_15_lut_out = L1_q_a[12];
B2_15 = DFFEAS(B2_15_lut_out, 40, CLRN, , , , , , );


--B2_16 is 74273b:3|16
--operation mode is normal

B2_16_lut_out = L1_q_a[11];
B2_16 = DFFEAS(B2_16_lut_out, 40, CLRN, , , , , , );


--B2_17 is 74273b:3|17
--operation mode is normal

B2_17_lut_out = L1_q_a[10];
B2_17 = DFFEAS(B2_17_lut_out, 40, CLRN, , , , , , );


--B2_18 is 74273b:3|18
--operation mode is normal

B2_18_lut_out = L1_q_a[9];
B2_18 = DFFEAS(B2_18_lut_out, 40, CLRN, , , , , , );


--B2_19 is 74273b:3|19
--operation mode is normal

B2_19_lut_out = L1_q_a[8];
B2_19 = DFFEAS(B2_19_lut_out, 40, CLRN, , , , , , );


--B4_13 is 74273b:21|13
--operation mode is normal

B4_13_lut_out = L1_q_a[22];
B4_13 = DFFEAS(B4_13_lut_out, 40, CLRN, , , , , , );


--B4_14 is 74273b:21|14
--operation mode is normal

B4_14_lut_out = L1_q_a[21];
B4_14 = DFFEAS(B4_14_lut_out, 40, CLRN, , , , , , );


--B4_15 is 74273b:21|15
--operation mode is normal

B4_15_lut_out = L1_q_a[20];
B4_15 = DFFEAS(B4_15_lut_out, 40, CLRN, , , , , , );


--B4_16 is 74273b:21|16
--operation mode is normal

B4_16_lut_out = L1_q_a[19];
B4_16 = DFFEAS(B4_16_lut_out, 40, CLRN, , , , , , );


--B4_17 is 74273b:21|17
--operation mode is normal

B4_17_lut_out = L1_q_a[18];
B4_17 = DFFEAS(B4_17_lut_out, 40, CLRN, , , , , , );


--B4_18 is 74273b:21|18
--operation mode is normal

B4_18_lut_out = L1_q_a[17];
B4_18 = DFFEAS(B4_18_lut_out, 40, CLRN, , , , , , );


--B4_19 is 74273b:21|19
--operation mode is normal

B4_19_lut_out = L1_q_a[16];
B4_19 = DFFEAS(B4_19_lut_out, 40, CLRN, , , , , , );


--Y3L2 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~156
--operation mode is arithmetic

Y3L2_carry_eqn = Y3L5;
Y3L2 = B8_12 $ B7_12 $ Y3L2_carry_eqn;

--Y3L3 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~158
--operation mode is arithmetic

Y3L3 = CARRY(B8_12 & !B7_12 & !Y3L5 # !B8_12 & (!Y3L5 # !B7_12));


--G1_11 is dcf:84|11
--operation mode is normal

G1_11_lut_out = VCC;
G1_11 = DFFEAS(G1_11_lut_out, VCC, !A1L31, , , VCC, !START, , );


--BB1_11 is sequence:103|74393b:25|11
--operation mode is normal

BB1_11 = BB1_1 & BB1_3 & BB1_5;


--BB1L4 is sequence:103|74393b:25|8~9
--operation mode is normal

BB1L4 = BB1_1 & BB1_3;


--L1_q_a[23] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[23]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[23]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[23]_PORT_A_address_reg = DFFE(L1_q_a[23]_PORT_A_address, L1_q_a[23]_clock_0, , , );
L1_q_a[23]_clock_0 = CLK;
L1_q_a[23]_PORT_A_data_out = MEMORY(, , L1_q_a[23]_PORT_A_address_reg, , , , , , L1_q_a[23]_clock_0, , , , , );
L1_q_a[23]_PORT_A_data_out_reg = DFFE(L1_q_a[23]_PORT_A_data_out, L1_q_a[23]_clock_0, , , );
L1_q_a[23] = L1_q_a[23]_PORT_A_data_out_reg[0];


--40 is 40
--operation mode is normal

40 = J1_37 & CLK;


--L1_q_a[13] is lpm_rom0:7|altsyncram:altsyncram_component|altsyncram_b7r:auto_generated|q_a[13]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
L1_q_a[13]_PORT_A_address = BUS(M1_9, M1_87, M1_99, M1_110, B3_15, B3_14, 24, 25);
L1_q_a[13]_PORT_A_address_reg = DFFE(L1_q_a[13]_PORT_A_address, L1_q_a[13]_clock_0, , , );
L1_q_a[13]_clock_0 = CLK;
L1_q_a[13]_PORT_A_data_out = MEMORY(, , L1_q_a[13]_PORT_A_address_reg, , , , , , L1_q_a[13]_clock_0, , , , , );
L1_q_a[13]_PORT_A_data_out_reg = DFFE(L1_q_a[13]_PORT_A_data_out, L1_q_a[13]_clock_0, , , );
L1_q_a[13] = L1_q_a[13]_PORT_A_data_out_reg[0];


--M3L81 is 8cpu:92|pc:65|74161:9|f74161:sub|110~COMBOUT
--operation mode is normal

M3L81 = U4L91 & (M3_110) # !U4L91 & U4L81;

--M3_110 is 8cpu:92|pc:65|74161:9|f74161:sub|110
--operation mode is normal

M3_110 = DFFEAS(M3L81, H1L3, CLRN, , , M3_107, , , 61);


--H1_12 is 8cpu:92|12
--operation mode is normal

H1_12 = J1L2 & B1_19 & CLK;


--M3L51 is 8cpu:92|pc:65|74161:9|f74161:sub|99~COMBOUT
--operation mode is normal

M3L51 = U4L91 & (M3_99) # !U4L91 & U4L41;

--M3_99 is 8cpu:92|pc:65|74161:9|f74161:sub|99
--operation mode is normal

M3_99 = DFFEAS(M3L51, H1L3, CLRN, , , M3L31, , , 61);


--M3L11 is 8cpu:92|pc:65|74161:9|f74161:sub|87~COMBOUT
--operation mode is normal

M3L11 = U4L91 & (M3_87) # !U4L91 & U4L21;

--M3_87 is 8cpu:92|pc:65|74161:9|f74161:sub|87
--operation mode is normal

M3_87 = DFFEAS(M3L11, H1L3, CLRN, , , M3L9, , , 61);


--M3L2 is 8cpu:92|pc:65|74161:9|f74161:sub|9~COMBOUT
--operation mode is normal

M3L2 = U4L91 & (M3_9) # !U4L91 & U4L01;

--M3_9 is 8cpu:92|pc:65|74161:9|f74161:sub|9
--operation mode is normal

M3_9 = DFFEAS(M3L2, H1L3, CLRN, , , M3L4, , , 61);


--M2L71 is 8cpu:92|pc:65|74161:8|f74161:sub|110~COMBOUT
--operation mode is normal

M2L71 = U4L91 & (M2_110) # !U4L91 & U4L8;

--M2_110 is 8cpu:92|pc:65|74161:8|f74161:sub|110
--operation mode is normal

M2_110 = DFFEAS(M2L71, H1L3, CLRN, , , M2L51, , , 61);


--M2L31 is 8cpu:92|pc:65|74161:8|f74161:sub|99~COMBOUT
--operation mode is normal

M2L31 = U4L91 & (M2_99) # !U4L91 & U4L6;

--M2_99 is 8cpu:92|pc:65|74161:8|f74161:sub|99
--operation mode is normal

M2_99 = DFFEAS(M2L31, H1L3, CLRN, , , M2L11, , , 61);


--M2L9 is 8cpu:92|pc:65|74161:8|f74161:sub|87~COMBOUT
--operation mode is normal

M2L9 = U4L91 & (M2_87) # !U4L91 & U4L4;

--M2_87 is 8cpu:92|pc:65|74161:8|f74161:sub|87
--operation mode is normal