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--B3_17 is 74273b:10|17
--operation mode is normal

B3_17_lut_out = M2L31;
B3_17 = DFFEAS(B3_17_lut_out, 19, !76, , , , , , );


--68 is 68
--operation mode is normal

68 = B2_15 & (B3_17 # B2_16 & B3_19) # !B2_15 & B2_16 & B3_19;


--B3_18 is 74273b:10|18
--operation mode is normal

B3_18_lut_out = M2L9;
B3_18 = DFFEAS(B3_18_lut_out, 19, !76, , , , , , );


--B3_16 is 74273b:10|16
--operation mode is normal

B3_16_lut_out = M2L71;
B3_16 = DFFEAS(B3_16_lut_out, 19, !76, , , , , , );


--69 is 69
--operation mode is normal

69 = B2_15 & (B3_16 # B2_16 & B3_18) # !B2_15 & B2_16 & B3_18;


--Z1L72 is 8cpu:92|bi74670:67|74670c:32|126~11
--operation mode is normal

Z1L72 = 68 & (69) # !68 & (69 & Z1_86 # !69 & (Z1_95));


--Z1L82 is 8cpu:92|bi74670:67|74670c:32|126~12
--operation mode is normal

Z1L82 = 68 & (Z1L72 & (Z1_76) # !Z1L72 & Z1_85) # !68 & (Z1L72);


--U4L51 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~86
--operation mode is normal

U4L51 = J1L2 & (B1_15 # B1_12 & B1_13);


--B9_12 is 8cpu:92|alu:62|74273b:11|12
--operation mode is normal

B9_12_lut_out = Y3L2;
B9_12 = DFFEAS(B9_12_lut_out, P1_22, VCC, , , , , , );


--U4L61 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~87
--operation mode is normal

U4L61 = J1L2 & B1_13 & (!B1_15);


--AB1_q_a[7] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[7]_PORT_A_data_in = M3L81;
AB1_q_a[7]_PORT_A_data_in_reg = DFFE(AB1_q_a[7]_PORT_A_data_in, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[7]_PORT_B_address_reg = DFFE(AB1_q_a[7]_PORT_B_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_PORT_A_write_enable = 70;
AB1_q_a[7]_PORT_A_write_enable_reg = DFFE(AB1_q_a[7]_PORT_A_write_enable, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = CLK;
AB1_q_a[7]_PORT_A_data_out = MEMORY(AB1_q_a[7]_PORT_A_data_in_reg, , AB1_q_a[7]_PORT_A_address_reg, AB1_q_a[7]_PORT_B_address_reg, AB1_q_a[7]_PORT_A_write_enable_reg, , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7] = AB1_q_a[7]_PORT_A_data_out_reg[0];


--U4L71 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~88
--operation mode is normal

U4L71 = U4L51 & (U4L61) # !U4L51 & (U4L61 & B9_12 # !U4L61 & (AB1_q_a[7]));


--U4L81 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~89
--operation mode is normal

U4L81 = U4L51 & (U4L71 & (kdata[8]) # !U4L71 & Z1L82) # !U4L51 & (U4L71);


--U4L91 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~90
--operation mode is normal

U4L91 = J1L2 & B1_14 & B1_15;


--B9_13 is 8cpu:92|alu:62|74273b:11|13
--operation mode is normal

B9_13_lut_out = Y3L4;
B9_13 = DFFEAS(B9_13_lut_out, P1_22, VCC, , , , , , );


--Z1L52 is 8cpu:92|bi74670:67|74670c:32|121~11
--operation mode is normal

Z1L52 = 69 & (68) # !69 & (68 & Z1_66 # !68 & (Z1_56));


--Z1L62 is 8cpu:92|bi74670:67|74670c:32|121~12
--operation mode is normal

Z1L62 = 69 & (Z1L52 & (Z1_75) # !Z1L52 & Z1_65) # !69 & (Z1L52);


--AB1_q_a[6] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[6]_PORT_A_data_in = M3L51;
AB1_q_a[6]_PORT_A_data_in_reg = DFFE(AB1_q_a[6]_PORT_A_data_in, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[6]_PORT_A_address_reg = DFFE(AB1_q_a[6]_PORT_A_address, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[6]_PORT_B_address_reg = DFFE(AB1_q_a[6]_PORT_B_address, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6]_PORT_A_write_enable = 70;
AB1_q_a[6]_PORT_A_write_enable_reg = DFFE(AB1_q_a[6]_PORT_A_write_enable, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6]_clock_0 = CLK;
AB1_q_a[6]_PORT_A_data_out = MEMORY(AB1_q_a[6]_PORT_A_data_in_reg, , AB1_q_a[6]_PORT_A_address_reg, AB1_q_a[6]_PORT_B_address_reg, AB1_q_a[6]_PORT_A_write_enable_reg, , , , AB1_q_a[6]_clock_0, , , , , );
AB1_q_a[6]_PORT_A_data_out_reg = DFFE(AB1_q_a[6]_PORT_A_data_out, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6] = AB1_q_a[6]_PORT_A_data_out_reg[0];


--U4L31 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~16
--operation mode is normal

U4L31 = U4L61 & (U4L51) # !U4L61 & (U4L51 & Z1L62 # !U4L51 & (AB1_q_a[6]));


--U4L41 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~17
--operation mode is normal

U4L41 = U4L61 & (U4L31 & (kdata[7]) # !U4L31 & B9_13) # !U4L61 & (U4L31);


--M3L31 is 8cpu:92|pc:65|74161:9|f74161:sub|95~0
--operation mode is arithmetic

M3L31_carry_eqn = M3_85;
M3L31 = M3_99 $ (M3L7 & M3L31_carry_eqn);

--M3_95 is 8cpu:92|pc:65|74161:9|f74161:sub|95
--operation mode is arithmetic

M3_95 = CARRY(!M3_85 # !M3_99);


--Z1L32 is 8cpu:92|bi74670:67|74670c:32|112~11
--operation mode is normal

Z1L32 = 68 & (69) # !68 & (69 & Z1_40 # !69 & (Z1_51));


--Z1L42 is 8cpu:92|bi74670:67|74670c:32|112~12
--operation mode is normal

Z1L42 = 68 & (Z1L32 & (Z1_30) # !Z1L32 & Z1_39) # !68 & (Z1L32);


--B9_14 is 8cpu:92|alu:62|74273b:11|14
--operation mode is normal

B9_14_lut_out = Y3L6;
B9_14 = DFFEAS(B9_14_lut_out, P1_22, VCC, , , , , , );


--AB1_q_a[5] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[5]_PORT_A_data_in = M3L11;
AB1_q_a[5]_PORT_A_data_in_reg = DFFE(AB1_q_a[5]_PORT_A_data_in, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[5]_PORT_A_address_reg = DFFE(AB1_q_a[5]_PORT_A_address, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[5]_PORT_B_address_reg = DFFE(AB1_q_a[5]_PORT_B_address, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5]_PORT_A_write_enable = 70;
AB1_q_a[5]_PORT_A_write_enable_reg = DFFE(AB1_q_a[5]_PORT_A_write_enable, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5]_clock_0 = CLK;
AB1_q_a[5]_PORT_A_data_out = MEMORY(AB1_q_a[5]_PORT_A_data_in_reg, , AB1_q_a[5]_PORT_A_address_reg, AB1_q_a[5]_PORT_B_address_reg, AB1_q_a[5]_PORT_A_write_enable_reg, , , , AB1_q_a[5]_clock_0, , , , , );
AB1_q_a[5]_PORT_A_data_out_reg = DFFE(AB1_q_a[5]_PORT_A_data_out, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5] = AB1_q_a[5]_PORT_A_data_out_reg[0];


--U4L11 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~16
--operation mode is normal

U4L11 = U4L51 & (U4L61) # !U4L51 & (U4L61 & B9_14 # !U4L61 & (AB1_q_a[5]));


--U4L21 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~17
--operation mode is normal

U4L21 = U4L51 & (U4L11 & (kdata[6]) # !U4L11 & Z1L42) # !U4L51 & (U4L11);


--M3L9 is 8cpu:92|pc:65|74161:9|f74161:sub|85~0
--operation mode is arithmetic

M3L9_carry_eqn = M3_81;
M3L9 = M3_87 $ (M3L7 & !M3L9_carry_eqn);

--M3_85 is 8cpu:92|pc:65|74161:9|f74161:sub|85
--operation mode is arithmetic

M3_85 = CARRY(M3_87 & (!M3_81));


--B9_15 is 8cpu:92|alu:62|74273b:11|15
--operation mode is normal

B9_15_lut_out = Y3L8;
B9_15 = DFFEAS(B9_15_lut_out, P1_22, VCC, , , , , , );


--Z1L12 is 8cpu:92|bi74670:67|74670c:32|107~11
--operation mode is normal

Z1L12 = 69 & (68) # !69 & (68 & Z1_20 # !68 & (Z1_5));


--Z1L22 is 8cpu:92|bi74670:67|74670c:32|107~12
--operation mode is normal

Z1L22 = 69 & (Z1L12 & (Z1_29) # !Z1L12 & Z1_19) # !69 & (Z1L12);


--AB1_q_a[4] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[4]_PORT_A_data_in = M3L2;
AB1_q_a[4]_PORT_A_data_in_reg = DFFE(AB1_q_a[4]_PORT_A_data_in, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[4]_PORT_A_address_reg = DFFE(AB1_q_a[4]_PORT_A_address, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[4]_PORT_B_address_reg = DFFE(AB1_q_a[4]_PORT_B_address, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4]_PORT_A_write_enable = 70;
AB1_q_a[4]_PORT_A_write_enable_reg = DFFE(AB1_q_a[4]_PORT_A_write_enable, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4]_clock_0 = CLK;
AB1_q_a[4]_PORT_A_data_out = MEMORY(AB1_q_a[4]_PORT_A_data_in_reg, , AB1_q_a[4]_PORT_A_address_reg, AB1_q_a[4]_PORT_B_address_reg, AB1_q_a[4]_PORT_A_write_enable_reg, , , , AB1_q_a[4]_clock_0, , , , , );
AB1_q_a[4]_PORT_A_data_out_reg = DFFE(AB1_q_a[4]_PORT_A_data_out, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4] = AB1_q_a[4]_PORT_A_data_out_reg[0];


--U4L9 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~16
--operation mode is normal

U4L9 = U4L61 & (U4L51) # !U4L61 & (U4L51 & Z1L22 # !U4L51 & (AB1_q_a[4]));


--U4L01 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~17
--operation mode is normal

U4L01 = U4L61 & (U4L9 & (kdata[5]) # !U4L9 & B9_15) # !U4L61 & (U4L9);


--M3L4 is 8cpu:92|pc:65|74161:9|f74161:sub|81~0
--operation mode is arithmetic

M3L4_carry_eqn = M3L6;
M3L4 = M3_9 $ (M3L4_carry_eqn);

--M3_81 is 8cpu:92|pc:65|74161:9|f74161:sub|81
--operation mode is arithmetic

M3_81 = CARRY(!M3L6 # !M3_9);


--Z2L32 is 8cpu:92|bi74670:67|74670c:34|126~11
--operation mode is normal

Z2L32 = 68 & (69) # !68 & (69 & Z2_86 # !69 & (Z2_95));


--Z2L42 is 8cpu:92|bi74670:67|74670c:34|126~12
--operation mode is normal

Z2L42 = 68 & (Z2L32 & (Z2_76) # !Z2L32 & Z2_85) # !68 & (Z2L32);


--B9_16 is 8cpu:92|alu:62|74273b:11|16
--operation mode is normal

B9_16_lut_out = Y3L01;
B9_16 = DFFEAS(B9_16_lut_out, P1_22, VCC, , , , , , );


--AB1_q_a[3] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[3]_PORT_A_data_in = M2L71;
AB1_q_a[3]_PORT_A_data_in_reg = DFFE(AB1_q_a[3]_PORT_A_data_in, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[3]_PORT_A_address_reg = DFFE(AB1_q_a[3]_PORT_A_address, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[3]_PORT_B_address_reg = DFFE(AB1_q_a[3]_PORT_B_address, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3]_PORT_A_write_enable = 70;
AB1_q_a[3]_PORT_A_write_enable_reg = DFFE(AB1_q_a[3]_PORT_A_write_enable, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3]_clock_0 = CLK;
AB1_q_a[3]_PORT_A_data_out = MEMORY(AB1_q_a[3]_PORT_A_data_in_reg, , AB1_q_a[3]_PORT_A_address_reg, AB1_q_a[3]_PORT_B_address_reg, AB1_q_a[3]_PORT_A_write_enable_reg, , , , AB1_q_a[3]_clock_0, , , , , );
AB1_q_a[3]_PORT_A_data_out_reg = DFFE(AB1_q_a[3]_PORT_A_data_out, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3] = AB1_q_a[3]_PORT_A_data_out_reg[0];


--U4L7 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~16
--operation mode is normal

U4L7 = U4L51 & (U4L61) # !U4L51 & (U4L61 & B9_16 # !U4L61 & (AB1_q_a[3]));


--U4L8 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~17
--operation mode is normal

U4L8 = U4L51 & (U4L7 & (kdata[4]) # !U4L7 & Z2L42) # !U4L51 & (U4L7);


--M2L51 is 8cpu:92|pc:65|74161:8|f74161:sub|105~0
--operation mode is arithmetic

M2L51_carry_eqn = M2_95;
M2L51 = M2_110 $ (M2L51_carry_eqn);

--M2_105 is 8cpu:92|pc:65|74161:8|f74161:sub|105
--operation mode is arithmetic

M2_105 = CARRY(!M2_95 # !M2_110);


--B9_17 is 8cpu:92|alu:62|74273b:11|17
--operation mode is normal

B9_17_lut_out = Y3L21;
B9_17 = DFFEAS(B9_17_lut_out, P1_22, VCC, , , , , , );


--Z2L12 is 8cpu:92|bi74670:67|74670c:34|121~11
--operation mode is normal

Z2L12 = 69 & (68) # !69 & (68 & Z2_66 # !68 & (Z2_56));


--Z2L22 is 8cpu:92|bi74670:67|74670c:34|121~12
--operation mode is normal

Z2L22 = 69 & (Z2L12 & (Z2_75) # !Z2L12 & Z2_65) # !69 & (Z2L12);


--AB1_q_a[2] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[2]_PORT_A_data_in = M2L31;
AB1_q_a[2]_PORT_A_data_in_reg = DFFE(AB1_q_a[2]_PORT_A_data_in, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[2]_PORT_A_address_reg = DFFE(AB1_q_a[2]_PORT_A_address, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[2]_PORT_B_address_reg = DFFE(AB1_q_a[2]_PORT_B_address, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2]_PORT_A_write_enable = 70;
AB1_q_a[2]_PORT_A_write_enable_reg = DFFE(AB1_q_a[2]_PORT_A_write_enable, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2]_clock_0 = CLK;
AB1_q_a[2]_PORT_A_data_out = MEMORY(AB1_q_a[2]_PORT_A_data_in_reg, , AB1_q_a[2]_PORT_A_address_reg, AB1_q_a[2]_PORT_B_address_reg, AB1_q_a[2]_PORT_A_write_enable_reg, , , , AB1_q_a[2]_clock_0, , , , , );
AB1_q_a[2]_PORT_A_data_out_reg = DFFE(AB1_q_a[2]_PORT_A_data_out, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2] = AB1_q_a[2]_PORT_A_data_out_reg[0];


--U4L5 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~16
--operation mode is normal

U4L5 = U4L61 & (U4L51) # !U4L61 & (U4L51 & Z2L22 # !U4L51 & (AB1_q_a[2]));


--U4L6 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~17
--operation mode is normal

U4L6 = U4L61 & (U4L5 & (kdata[3]) # !U4L5 & B9_17) # !U4L61 & (U4L5);


--M2L11 is 8cpu:92|pc:65|74161:8|f74161:sub|95~0
--operation mode is arithmetic

M2L11_carry_eqn = M2_85;
M2L11 = M2_99 $ (!M2L11_carry_eqn);

--M2_95 is 8cpu:92|pc:65|74161:8|f74161:sub|95
--operation mode is arithmetic

M2_95 = CARRY(M2_99 & (!M2_85));


--Z2L91 is 8cpu:92|bi74670:67|74670c:34|112~11
--operation mode is normal

Z2L91 = 68 & (69) # !68 & (69 & Z2_40 # !69 & (Z2_51));


--Z2L02 is 8cpu:92|bi74670:67|74670c:34|112~12
--operation mode is normal

Z2L02 = 68 & (Z2L91 & (Z2_30) # !Z2L91 & Z2_39) # !68 & (Z2L91);


--B9_18 is 8cpu:92|alu:62|74273b:11|18
--operation mode is normal

B9_18_lut_out = Y3L41;
B9_18 = DFFEAS(B9_18_lut_out, P1_22, VCC, , , , , , );


--AB1_q_a[1] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_td41:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[1]_PORT_A_data_in = M2L9;
AB1_q_a[1]_PORT_A_data_in_reg = DFFE(AB1_q_a[1]_PORT_A_data_in, AB1_q_a[1]_clock_0, , , );
AB1_q_a[1]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[1]_PORT_A_address_reg = DFFE(AB1_q_a[1]_PORT_A_address, AB1_q_a[1]_clock_0, , , );
AB1_q_a[1]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
AB1_q_a[1]_PORT_B_address_reg = DFFE(AB1_q_a[1]_PORT_B_address, AB1_q_a[1]_clock_0, , , );
AB1_q_a[1]_PORT_A_write_enable = 70;
AB1_q_a[1]_PORT_A_write_enable_reg = DFFE(AB1_q_a[1]_PORT_A_write_enable, AB1_q_a[1]_clock_0, , , );
AB1_q_a[1]_clock_0 = CLK;

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