/* *  linux/include/asm-arm/arch-pxa/pxa-regs.h * *  Author:	Nicolas Pitre *  Created:	Jun 15, 2001 *  Copyright:	MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions. *   Added include for hardware.h (for __REG definition) */#ifndef _PXA_REGS_H_#define _PXA_REGS_H_#include "bitfield.h"#include "hardware.h"/* FIXME hack so that SA-1111.h will work [cb] */#ifndef __ASSEMBLY__typedef unsigned short	Word16 ;typedef unsigned int	Word32 ;typedef Word32		Word ;typedef Word		Quad [4] ;typedef void		*Address ;typedef void		(*ExcpHndlr) (void) ;#endif/* * PXA Chip selects */#ifdef CONFIG_CPU_MONAHANS#define PXA_CS0_PHYS   0x00000000 /* for both small and large same start */#define PXA_CS1_PHYS   0x04000000 /* Small partition start address (64MB) */#define PXA_CS1_LPHYS  0x30000000 /* Large partition start address (256MB) */#define PXA_CS2_PHYS   0x10000000 /* (64MB) */#define PXA_CS3_PHYS   0x14000000 /* (64MB) */#define PXA_PCMCIA_PHYS        0x20000000 /* (256MB) */#else#define PXA_CS0_PHYS	0x00000000#define PXA_CS1_PHYS	0x04000000#define PXA_CS2_PHYS	0x08000000#define PXA_CS3_PHYS	0x0C000000#define PXA_CS4_PHYS	0x10000000#define PXA_CS5_PHYS	0x14000000#endif /* CONFIG_CPU_MONAHANS *//* * Personal Computer Memory Card International Association (PCMCIA) sockets */#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */#define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */#endif#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \			(0x20000000 + (Nb)*PCMCIASp)#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */#define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */#define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */#endif/* * DMA Controller */#define DCSR0		__REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */#define DCSR1		__REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */#define DCSR2		__REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */#define DCSR3		__REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */#define DCSR4		__REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */#define DCSR5		__REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */#define DCSR6		__REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */#define DCSR7		__REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */#define DCSR8		__REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */#define DCSR9		__REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */#define DCSR10		__REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */#define DCSR11		__REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */#define DCSR12		__REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */#define DCSR13		__REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */#define DCSR14		__REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */#define DCSR15		__REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */#ifdef CONFIG_CPU_MONAHANS#define DCSR16		__REG(0x40000040)  /* DMA Control / Status Register for Channel 16 */#define DCSR17		__REG(0x40000044)  /* DMA Control / Status Register for Channel 17 */#define DCSR18		__REG(0x40000048)  /* DMA Control / Status Register for Channel 18 */#define DCSR19		__REG(0x4000004c)  /* DMA Control / Status Register for Channel 19 */#define DCSR20		__REG(0x40000050)  /* DMA Control / Status Register for Channel 20 */#define DCSR21		__REG(0x40000054)  /* DMA Control / Status Register for Channel 21 */#define DCSR22		__REG(0x40000058)  /* DMA Control / Status Register for Channel 22 */#define DCSR23		__REG(0x4000005c)  /* DMA Control / Status Register for Channel 23 */#define DCSR24		__REG(0x40000060)  /* DMA Control / Status Register for Channel 24 */#define DCSR25		__REG(0x40000064)  /* DMA Control / Status Register for Channel 25 */#define DCSR26		__REG(0x40000068)  /* DMA Control / Status Register for Channel 26 */#define DCSR27		__REG(0x4000006c)  /* DMA Control / Status Register for Channel 27 */#define DCSR28		__REG(0x40000070)  /* DMA Control / Status Register for Channel 28 */#define DCSR29		__REG(0x40000074)  /* DMA Control / Status Register for Channel 29 */#define DCSR30		__REG(0x40000078)  /* DMA Control / Status Register for Channel 30 */#define DCSR31		__REG(0x4000007c)  /* DMA Control / Status Register for Channel 31 */#endif /* CONFIG_CPU_MONAHANS */#define DCSR(x)		__REG2(0x40000000, (x) << 2)#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)#define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */#define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */#define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */#define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */#define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */#endif#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */#define DINT		__REG(0x400000f0)  /* DMA Interrupt Register */#define DRCMR0		__REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */#define DRCMR1		__REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */#define DRCMR2		__REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */#define DRCMR3		__REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */#define DRCMR4		__REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */#define DRCMR5		__REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */#define DRCMR6		__REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */#define DRCMR7		__REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */#define DRCMR8		__REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */#define DRCMR9		__REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */#define DRCMR10		__REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */#define DRCMR11		__REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */#define DRCMR12		__REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */#define DRCMR13		__REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */#define DRCMR14		__REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */#define DRCMR15		__REG(0x4000013c)  /* Reserved */#define DRCMR16		__REG(0x40000140)  /* Reserved */#define DRCMR17		__REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */#define DRCMR18		__REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */#define DRCMR19		__REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */#define DRCMR20		__REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */#define DRCMR21		__REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */#define DRCMR22		__REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */#define DRCMR23		__REG(0x4000015c)  /* Reserved */#define DRCMR24		__REG(0x40000160)  /* Reserved */#define DRCMR25		__REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */#define DRCMR26		__REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */#define DRCMR27		__REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */#define DRCMR28		__REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */#define DRCMR29		__REG(0x40000174)  /* Reserved */#define DRCMR30		__REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */#define DRCMR31		__REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */#define DRCMR32		__REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */#define DRCMR33		__REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */#define DRCMR34		__REG(0x40000188)  /* Reserved */#define DRCMR35		__REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */#define DRCMR36		__REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */#define DRCMR37		__REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */#define DRCMR38		__REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */#define DRCMR39		__REG(0x4000019C)  /* Reserved */#define DRCMR68		       __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */#define DRCMR69		       __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */#define DRCMR70		       __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */#define DRCMRRXSADR	DRCMR2#define DRCMRTXSADR	DRCMR3#define DRCMRRXBTRBR	DRCMR4#define DRCMRTXBTTHR	DRCMR5#define DRCMRRXFFRBR	DRCMR6#define DRCMRTXFFTHR	DRCMR7#define DRCMRRXMCDR	DRCMR8#define DRCMRRXMODR	DRCMR9#define DRCMRTXMODR	DRCMR10#define DRCMRRXPCDR	DRCMR11#define DRCMRTXPCDR	DRCMR12#define DRCMRRXSSDR	DRCMR13#define DRCMRTXSSDR	DRCMR14#define DRCMRRXICDR	DRCMR17#define DRCMRTXICDR	DRCMR18#define DRCMRRXSTRBR	DRCMR19#define DRCMRTXSTTHR	DRCMR20#define DRCMRRXMMC	DRCMR21#define DRCMRTXMMC	DRCMR22#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */#define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */#define DDADR0		__REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */#define DSADR0		__REG(0x40000204)  /* DMA Source Address Register Channel 0 */#define DTADR0		__REG(0x40000208)  /* DMA Target Address Register Channel 0 */#define DCMD0		__REG(0x4000020c)  /* DMA Command Address Register Channel 0 */#define DDADR1		__REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */#define DSADR1		__REG(0x40000214)  /* DMA Source Address Register Channel 1 */#define DTADR1		__REG(0x40000218)  /* DMA Target Address Register Channel 1 */#define DCMD1		__REG(0x4000021c)  /* DMA Command Address Register Channel 1 */#define DDADR2		__REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */#define DSADR2		__REG(0x40000224)  /* DMA Source Address Register Channel 2 */#define DTADR2		__REG(0x40000228)  /* DMA Target Address Register Channel 2 */#define DCMD2		__REG(0x4000022c)  /* DMA Command Address Register Channel 2 */#define DDADR3		__REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */#define DSADR3		__REG(0x40000234)  /* DMA Source Address Register Channel 3 */#define DTADR3		__REG(0x40000238)  /* DMA Target Address Register Channel 3 */#define DCMD3		__REG(0x4000023c)  /* DMA Command Address Register Channel 3 */#define DDADR4		__REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */#define DSADR4		__REG(0x40000244)  /* DMA Source Address Register Channel 4 */#define DTADR4		__REG(0x40000248)  /* DMA Target Address Register Channel 4 */#define DCMD4		__REG(0x4000024c)  /* DMA Command Address Register Channel 4 */#define DDADR5		__REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */#define DSADR5		__REG(0x40000254)  /* DMA Source Address Register Channel 5 */#define DTADR5		__REG(0x40000258)  /* DMA Target Address Register Channel 5 */#define DCMD5		__REG(0x4000025c)  /* DMA Command Address Register Channel 5 */#define DDADR6		__REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */#define DSADR6		__REG(0x40000264)  /* DMA Source Address Register Channel 6 */#define DTADR6		__REG(0x40000268)  /* DMA Target Address Register Channel 6 */#define DCMD6		__REG(0x4000026c)  /* DMA Command Address Register Channel 6 */#define DDADR7		__REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */#define DSADR7		__REG(0x40000274)  /* DMA Source Address Register Channel 7 */#define DTADR7		__REG(0x40000278)  /* DMA Target Address Register Channel 7 */#define DCMD7		__REG(0x4000027c)  /* DMA Command Address Register Channel 7 */#define DDADR8		__REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */#define DSADR8		__REG(0x40000284)  /* DMA Source Address Register Channel 8 */#define DTADR8		__REG(0x40000288)  /* DMA Target Address Register Channel 8 */#define DCMD8		__REG(0x4000028c)  /* DMA Command Address Register Channel 8 */#define DDADR9		__REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */#define DSADR9		__REG(0x40000294)  /* DMA Source Address Register Channel 9 */#define DTADR9		__REG(0x40000298)  /* DMA Target Address Register Channel 9 */#define DCMD9		__REG(0x4000029c)  /* DMA Command Address Register Channel 9 */#define DDADR10		__REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */#define DSADR10		__REG(0x400002a4)  /* DMA Source Address Register Channel 10 */#define DTADR10		__REG(0x400002a8)  /* DMA Target Address Register Channel 10 */#define DCMD10		__REG(0x400002ac)  /* DMA Command Address Register Channel 10 */#define DDADR11		__REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */#define DSADR11		__REG(0x400002b4)  /* DMA Source Address Register Channel 11 */#define DTADR11		__REG(0x400002b8)  /* DMA Target Address Register Channel 11 */#define DCMD11		__REG(0x400002bc)  /* DMA Command Address Register Channel 11 */#define DDADR12		__REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */#define DSADR12		__REG(0x400002c4)  /* DMA Source Address Register Channel 12 */#define DTADR12		__REG(0x400002c8)  /* DMA Target Address Register Channel 12 */#define DCMD12		__REG(0x400002cc)  /* DMA Command Address Register Channel 12 */