?? vectors.s
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;;; Copyright ARM Ltd 2002. All rights reserved.
AREA Vect, CODE, READONLY
; A vector table and dummy exception handlers
; *****************
; Exception Vectors
; *****************
; Note: LDR PC instructions are used here, though branch (B) instructions
; could also be used, unless the ROM is at an address >32MB.
ENTRY
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
DCD 0xb9205f80
LDR PC, [PC, #-0xff0]
LDR PC, FIQ_Addr
IMPORT Reset_Handler ; In init.s
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SWI_Addr DCD SWI_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
SPECIAL DCD 0
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
; ************************
; Exception Handlers
; ************************
; The following dummy handlers do not do anything useful in this example.
; They are set up here for completeness.
Undefined_Handler
B Undefined_Handler
SWI_Handler
B SWI_Handler
Prefetch_Handler
B Prefetch_Handler
Abort_Handler
B Abort_Handler
IMPORT IRQ_Exception
IRQ_Handler
B IRQ_Exception
IMPORT Fiq_Exception
FIQ_Handler
B Fiq_Exception
END
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