;;  Copyright ARM Ltd 2002. All rights reserved.
;;
;;  This code initialises the Integrator board (eg REMAP) before calling 
;;  TCM Initialization and MMU Initialization if they exist.
;;  this allows scatter loading to relocate code into the TCMs
;;
;;  This code must be run from a privileged mode


; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
  

  GET   LPC21xx.INC

  EXPORT __user_initial_stackheap  

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


 ; IF :DEF: ROM_RAM_REMAP
       
   



        AREA   INIT, CODE, READONLY   ; name this block of code
        
        

        EXPORT  Reset_Handler
Reset_Handler

 

            MRS     R2,  CPSR

; stack_base could be defined above, or located in a scatter file
        LDR     r0, stack_base ; 
       
        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ;閩い耞
        SUB     sp, r0, #Offset_SVC_Stack
; Enter each mode in turn and set up the stack pointer
        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ;閩い耞
        SUB     sp, r0, #Offset_FIQ_Stack

        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ;閩い耞
        SUB     sp, r0, #Offset_IRQ_Stack

        
        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ;閩い耞
        SUB     sp, r0, #Offset_ABT_Stack
 
        MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ;閩い耞
        SUB     sp, r0, #Offset_UND_Stack

 
     
        MSR     CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit ;閩い耞
        SUB     sp, r0, #Offset_USR_Stack
        
             
      ;  MSR     CPSR_c, #Mode_USR:OR:I_Bit:OR:F_Bit ;閩い耞
      ;  SUB     sp, r0, #Offset_USR_Stack        
     
      ;   MSR     CPSR_c, R2 ;  //