+----------------------------------+-----------------+------------------------+-----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                              ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------+
; ADC.v                            ; yes             ; User Verilog HDL File  ; F:/文件存儲/設計文件/Quartus II文件/verilog HDL/ADC/ADC.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Estimated Total logic elements              ; 23     ;
;                                             ;        ;
; Total combinational functions               ; 15     ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 4      ;
;     -- 3 input functions                    ; 3      ;
;     -- <=2 input functions                  ; 8      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 12     ;
;     -- arithmetic mode                      ; 3      ;
;                                             ;        ;
; Total registers                             ; 23     ;
;     -- Dedicated logic registers            ; 23     ;
;     -- I/O registers                        ; 0      ;
;                                             ;        ;
; I/O pins                                    ; 23     ;
; Maximum fan-out node                        ; clk1_r ;
; Maximum fan-out                             ; 19     ;
; Total fan-out                               ; 118    ;
; Average fan-out                             ; 1.93   ;
+---------------------------------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |ADC                       ; 15 (15)           ; 23 (23)      ; 0           ; 0            ; 0       ; 0         ; 23   ; 0            ; |ADC                ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------+
; State Machine - |ADC|state                                                        ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; Name      ; state.st5 ; state.st4 ; state.st3 ; state.st2 ; state.st1 ; state.st0 ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; state.st0 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ;
; state.st1 ; 0         ; 0         ; 0         ; 0         ; 1         ; 1         ;
; state.st2 ; 0         ; 0         ; 0         ; 1         ; 0         ; 1         ;
; state.st3 ; 0         ; 0         ; 1         ; 0         ; 0         ; 1         ;
; state.st4 ; 0         ; 1         ; 0         ; 0         ; 0         ; 1         ;
; state.st5 ; 1         ; 0         ; 0         ; 0         ; 0         ; 1         ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 23    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 15    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |ADC ;
+----------------+--------+-------------------------------------------+
; Parameter Name ; Value  ; Type                                      ;
+----------------+--------+-------------------------------------------+
; st0            ; 000001 ; Unsigned Binary                           ;
; st1            ; 000010 ; Unsigned Binary                           ;
; st2            ; 000100 ; Unsigned Binary                           ;
; st3            ; 001000 ; Unsigned Binary                           ;
; st4            ; 010000 ; Unsigned Binary                           ;
; st5            ; 100000 ; Unsigned Binary                           ;
+----------------+--------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sun May 24 14:44:33 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC
Info: Found 1 design units, including 1 entities, in source file ADC.v
    Info: Found entity 1: ADC
Info: Elaborating entity "ADC" for the top level hierarchy
Info: State machine "|ADC|state" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|ADC|state"
Info: Encoding result for state machine "|ADC|state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "state.st5"
        Info: Encoded state bit "state.st4"
        Info: Encoded state bit "state.st3"
        Info: Encoded state bit "state.st2"
        Info: Encoded state bit "state.st1"
        Info: Encoded state bit "state.st0"
    Info: State "|ADC|state.st0" uses code string "000000"
    Info: State "|ADC|state.st1" uses code string "000011"
    Info: State "|ADC|state.st2" uses code string "000101"
    Info: State "|ADC|state.st3" uses code string "001001"
    Info: State "|ADC|state.st4" uses code string "010001"
    Info: State "|ADC|state.st5" uses code string "100001"
Info: Generated suppressed messages file F:/文件存儲/設計文件/Quartus II文件/verilog HDL/ADC/ADC.map.smsg
Info: Implemented 48 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 12 output pins
    Info: Implemented 25 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 159 megabytes
    Info: Processing ended: Sun May 24 14:44:37 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:02


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/文件存儲/設計文件/Quartus II文件/verilog HDL/ADC/ADC.map.smsg.