LIBRARY		IEEE;
USE		IEEE.STD_LOGIC_1164.ALL;
USE		IEEE.STD_LOGIC_UNSIGNED.ALL;
USE		IEEE.STD_LOGIC_ARITH.ALL;

ENTITY	VC5402	IS
	PORT(
			RW			:IN		STD_LOGIC;
			PS			:IN		STD_LOGIC;
			DS			:IN		STD_LOGIC;			
			IOS			:IN		STD_LOGIC;
			IOSTRB	:IN		STD_LOGIC;
			MEMSTRB	:IN		STD_LOGIC;
			IRQ			:IN		STD_LOGIC;
			USBINT	:IN		STD_LOGIC;
			AH			:IN		STD_LOGIC_VECTOR(2 DOWNTO 0);-- A14,A13,A12 	
			MEMWR		:OUT	STD_LOGIC;
			MEMRD		:OUT	STD_LOGIC;
			IOWR		:OUT	STD_LOGIC;
			IORD		:OUT	STD_LOGIC;
			INT0		:OUT	STD_LOGIC;
			INT1		:OUT	STD_LOGIC;
			RAMCS		:OUT	STD_LOGIC;
			LCDCS		:OUT	STD_LOGIC;
			NETCS		:OUT	STD_LOGIC;
			USBCS		:OUT	STD_LOGIC;	
			NPS			:OUT	STD_LOGIC;
			KEYOE		:OUT	STD_LOGIC
		);
END VC5402;

ARCHITECTURE  AA  OF VC5402  IS
	SIGNAL	CS		:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN

	P0:PROCESS(IOS,AH(2 DOWNTO 0))
	BEGIN
		IF  IOS='0' 	THEN
			CASE	AH(2 DOWNTO 0)    IS
				WHEN "000"=> CS<="11111110";
				WHEN "001"=> CS<="11111101";
				WHEN "010"=> CS<="11111011";
				WHEN "011"=> CS<="11110111";
				WHEN "100"=> CS<="11101111";
				WHEN "101"=> CS<="11011111";
				WHEN "110"=> CS<="10111111";
				WHEN "111"=> CS<="01111111";
				WHEN OTHERS=> CS<="11111111";
			END CASE;
	   ELSE
			CS<="11111111";
	   END  IF;
	END PROCESS;  

	INT0 <= NOT (IRQ);
	INT1 <= USBINT;
	MEMWR<= RW OR DS;
	MEMRD<= NOT (RW) OR DS;
	IOWR <= RW OR IOS;
	IORD <= NOT (RW) OR IOS;
	KEYOE<= IOSTRB OR CS(0);
	RAMCS<= MEMSTRB OR DS;
	USBCS<= CS(1);
	NETCS<= CS(2);
	LCDCS<= CS(3);
    NPS<= NOT PS;
END  AA;