// Reading of the next receive buffer descriptor starts after reception status is// written to the previous one.// Latching READY status of the Rx buffer descriptoralways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxBDReady <=#Tp 1'b0;  else  if(RxPointerRead)    RxBDReady <=#Tp 1'b0;  else  if(RxEn & RxEn_q & RxBDRead)    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginningend// Latching Rx buffer descriptor status// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)always @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxStatus <=#Tp 2'h0;  else  if(RxEn & RxEn_q & RxBDRead)    RxStatus <=#Tp ram_do[14:13];end// RxReady generationalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxReady <=#Tp 1'b0;  else  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)    RxReady <=#Tp 1'b0;  else  if(RxEn & RxEn_q & RxPointerRead)    RxReady <=#Tp 1'b1;end// Reading Rx BD pointerassign StartRxPointerRead = RxBDRead & RxBDReady;// Reading Tx BD Pointeralways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxPointerRead <=#Tp 1'b0;  else  if(StartRxPointerRead)    RxPointerRead <=#Tp 1'b1;  else  if(RxEn & RxEn_q)    RxPointerRead <=#Tp 1'b0;end//Latching Rx buffer pointer from buffer descriptor;always @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxPointerMSB <=#Tp 30'h0;  else  if(RxEn & RxEn_q & RxPointerRead)    RxPointerMSB <=#Tp ram_do[31:2];  else  if(MasterWbRX & m_wb_ack_i)      RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)end//Latching last addresses from buffer descriptor (used as byte-half-word indicator);always @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxPointerLSB_rst[1:0] <=#Tp 0;  else  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active    RxPointerLSB_rst[1:0] <=#Tp 0;  else  if(RxEn & RxEn_q & RxPointerRead)    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];endalways @ (RxPointerLSB_rst)begin  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case    2'h0 : RxByteSel[3:0] = 4'hf;    2'h1 : RxByteSel[3:0] = 4'h7;    2'h2 : RxByteSel[3:0] = 4'h3;    2'h3 : RxByteSel[3:0] = 4'h1;  endcaseendalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxEn_needed <=#Tp 1'b0;  else  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)    RxEn_needed <=#Tp 1'b1;  else  if(RxPointerRead & RxEn & RxEn_q)    RxEn_needed <=#Tp 1'b0;end// Reception status is written back to the buffer descriptor after the end of frame is detected.assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;reg RxEnableWindow;// Indicating that last byte is being reveivedalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    LastByteIn <=#Tp 1'b0;  else  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)    LastByteIn <=#Tp 1'b0;  else  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)    LastByteIn <=#Tp 1'b1;endreg ShiftEnded_rck;reg ShiftEndedSync1;reg ShiftEndedSync2;reg ShiftEndedSync3;reg ShiftEndedSync_c1;reg ShiftEndedSync_c2;wire StartShiftWillEnd;assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;// Indicating that data reception will endalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    ShiftWillEnd <=#Tp 1'b0;  else  if(ShiftEnded_rck | RxAbort)    ShiftWillEnd <=#Tp 1'b0;  else  if(StartShiftWillEnd)    ShiftWillEnd <=#Tp 1'b1;end// Receive byte counteralways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    RxByteCnt <=#Tp 2'h0;  else  if(ShiftEnded_rck | RxAbort)    RxByteCnt <=#Tp 2'h0;  else  if(RxValid & RxStartFrm & RxReady)    case(RxPointerLSB_rst)  // synopsys parallel_case      2'h0 : RxByteCnt <=#Tp 2'h1;      2'h1 : RxByteCnt <=#Tp 2'h2;      2'h2 : RxByteCnt <=#Tp 2'h3;      2'h3 : RxByteCnt <=#Tp 2'h0;    endcase  else  if(RxValid & RxEnableWindow & RxReady | LastByteIn)    RxByteCnt <=#Tp RxByteCnt + 1'b1;end// Indicates how many bytes are valid within the last wordalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    RxValidBytes <=#Tp 2'h1;  else  if(RxValid & RxStartFrm)    case(RxPointerLSB_rst)  // synopsys parallel_case      2'h0 : RxValidBytes <=#Tp 2'h1;      2'h1 : RxValidBytes <=#Tp 2'h2;      2'h2 : RxValidBytes <=#Tp 2'h3;      2'h3 : RxValidBytes <=#Tp 2'h0;    endcase  else  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)    RxValidBytes <=#Tp RxValidBytes + 1'b1;endalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    RxDataLatched1       <=#Tp 24'h0;  else  if(RxValid & RxReady & ~LastByteIn)    if(RxStartFrm)    begin      case(RxPointerLSB_rst)     // synopsys parallel_case        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;      endcase    end    else if (RxEnableWindow)    begin      case(RxByteCnt)     // synopsys parallel_case        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;      endcase    endendwire SetWriteRxDataToFifo;// Assembling data that will be written to the rx_fifoalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    RxDataLatched2 <=#Tp 32'h0;  else  if(SetWriteRxDataToFifo & ~ShiftWillEnd)    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering  else  if(SetWriteRxDataToFifo & ShiftWillEnd)    case(RxValidBytes)  // synopsys parallel_case      0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],  RxData};       // Big Endian Byte Ordering      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};    endcaseendreg WriteRxDataToFifoSync1;reg WriteRxDataToFifoSync2;reg WriteRxDataToFifoSync3;// Indicating start of the reception processassign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |                               (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |                               (ShiftWillEnd & LastByteIn & (&RxByteCnt));always @ (posedge MRxClk or posedge Reset)begin  if(Reset)    WriteRxDataToFifo <=#Tp 1'b0;  else  if(SetWriteRxDataToFifo & ~RxAbort)    WriteRxDataToFifo <=#Tp 1'b1;  else  if(WriteRxDataToFifoSync2 | RxAbort)    WriteRxDataToFifo <=#Tp 1'b0;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    WriteRxDataToFifoSync1 <=#Tp 1'b0;  else  if(WriteRxDataToFifo)    WriteRxDataToFifoSync1 <=#Tp 1'b1;  else    WriteRxDataToFifoSync1 <=#Tp 1'b0;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    WriteRxDataToFifoSync2 <=#Tp 1'b0;  else    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    WriteRxDataToFifoSync3 <=#Tp 1'b0;  else    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;endwire WriteRxDataToFifo_wb;assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;reg LatchedRxStartFrm;reg SyncRxStartFrm;reg SyncRxStartFrm_q;reg SyncRxStartFrm_q2;wire RxFifoReset;always @ (posedge MRxClk or posedge Reset)begin  if(Reset)    LatchedRxStartFrm <=#Tp 0;  else  if(RxStartFrm & ~SyncRxStartFrm_q)    LatchedRxStartFrm <=#Tp 1;  else  if(SyncRxStartFrm_q)    LatchedRxStartFrm <=#Tp 0;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    SyncRxStartFrm <=#Tp 0;  else  if(LatchedRxStartFrm)    SyncRxStartFrm <=#Tp 1;  else    SyncRxStartFrm <=#Tp 0;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    SyncRxStartFrm_q <=#Tp 0;  else    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    SyncRxStartFrm_q2 <=#Tp 0;  else    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;endassign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),          .clk(WB_CLK_I),                                .reset(Reset),          .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),          .clear(RxFifoReset),                           .full(RxBufferFull),          .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),          .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)        );assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;assign WriteRxDataToMemory = ~RxBufferEmpty;assign rx_burst = rx_burst_en & WriteRxDataToMemory;// Generation of the end-of-frame signalalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    ShiftEnded_rck <=#Tp 1'b0;  else  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)    ShiftEnded_rck <=#Tp 1'b1;  else  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)    ShiftEnded_rck <=#Tp 1'b0;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    ShiftEndedSync1 <=#Tp 1'b0;  else    ShiftEndedSync1 <=#Tp ShiftEnded_rck;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    ShiftEndedSync2 <=#Tp 1'b0;  else    ShiftEndedSync2 <=#Tp ShiftEndedSync1;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    ShiftEndedSync3 <=#Tp 1'b0;  else  if(ShiftEndedSync1 & ~ShiftEndedSync2)    ShiftEndedSync3 <=#Tp 1'b1;  else  if(ShiftEnded)    ShiftEndedSync3 <=#Tp 1'b0;end// Generation of the end-of-frame signalalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    ShiftEnded <=#Tp 1'b0;  else  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)    ShiftEnded <=#Tp 1'b1;  else  if(RxStatusWrite)    ShiftEnded <=#Tp 1'b0;endalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    ShiftEndedSync_c1 <=#Tp 1'b0;  else    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;endalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    ShiftEndedSync_c2 <=#Tp 1'b0;  else    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;end// Generation of the end-of-frame signalalways @ (posedge MRxClk or posedge Reset)begin  if(Reset)    RxEnableWindow <=#Tp 1'b0;  else  if(RxStartFrm)    RxEnableWindow <=#Tp 1'b1;  else  if(RxEndFrm | RxAbort)    RxEnableWindow <=#Tp 1'b0;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxAbortSync1 <=#Tp 1'b0;  else    RxAbortSync1 <=#Tp RxAbortLatched;endalways @ (posedge WB_CLK_I or posedge Reset)begin  if(Reset)    RxAbortSync2 <=#Tp 1'b0;  else    RxAbortSync2