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<messages>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="863" delta="old" >The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFGP symbol &quot;Clk_in_BUFGP&quot; (output signal=Clk_in_BUFGP),
BUFGP symbol &quot;Start_in_BUFGP&quot; (output signal=Start_in_BUFGP),
BUFG symbol &quot;SubKeyMemory_0_not0001_BUFG&quot; (output signal=SubKeyMemory_0_not0001),
BUFG symbol &quot;SubKeyMemory_1_cmp_eq0000_BUFG&quot; (output signal=SubKeyMemory_1_cmp_eq0000),
BUFG symbol &quot;SubKeyMemory_2_cmp_eq0000_BUFG&quot; (output signal=SubKeyMemory_2_cmp_eq0000),
BUFG symbol &quot;SubKeyMemory_3_cmp_eq0000_BUFG&quot; (output signal=SubKeyMemory_3_cmp_eq0000)</arg>
</msg>

<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="LIT" num="175" delta="old" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_Start_in_BUFGP/Start_in_BUFGP/BUFG&quot; (output signal=Start_in_BUFGP)</arg> has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
<arg fmt="%s" index="2">Pin CE of EnableMKeyExt
Pin I2 of SelectPlace_out&lt;3&gt;1
Pin I0 of SelectPlace_out&lt;2&gt;1
Pin I0 of SelectPlace_out&lt;1&gt;1
Pin I1 of SelectPlace_out&lt;0&gt;1</arg>
</msg>

<msg type="warning" file="Pack" num="266" delta="old" >The function generator <arg fmt="%s" index="1">KeyExtend/Mxor_Addr_in_15_xo&lt;2&gt;1_G</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">KeyExtend/Mxor_Addr_in_15_xo&lt;2&gt;1</arg>.  <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">ShowDigit_out_mux0000&lt;7&gt;</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

</messages>