?? traffic.rpt
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Project Information f:\traffic\traffic.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/31/2009 19:19:51
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
traffic EP1K30TC144-1 4 54 0 0 0 % 289 16 %
User Pins: 4 54 0
Project Information f:\traffic\traffic.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
traffic@121 a
traffic@117 b
traffic@132 c
traffic@125 clk1
traffic@55 clk2
traffic@119 d
traffic@128 dp
traffic@112 e
traffic@131 f
traffic@110 g
traffic@88 green1
traffic@114 green2
traffic@98 green3
traffic@90 green4
traffic@87 green5
traffic@89 green6
traffic@95 green7
traffic@99 green8
traffic@36 green9
traffic@33 green10
traffic@29 green11
traffic@31 green12
traffic@30 green13
traffic@63 green14
traffic@68 green15
traffic@73 green16
traffic@72 manuctrl
traffic@133 out0
traffic@140 out1
traffic@135 out2
traffic@136 out3
traffic@141 out4
traffic@138 out5
traffic@80 red1
traffic@100 red2
traffic@102 red3
traffic@96 red4
traffic@83 red5
traffic@91 red6
traffic@97 red7
traffic@101 red8
traffic@32 red9
traffic@27 red10
traffic@65 red11
traffic@81 red12
traffic@28 red13
traffic@70 red14
traffic@79 red15
traffic@78 red16
traffic@51 row1
traffic@59 row2
traffic@60 row3
traffic@48 row4
traffic@46 row5
traffic@43 row6
traffic@41 row7
traffic@38 row8
traffic@64 rst
Project Information f:\traffic\traffic.rpt
** FILE HIERARCHY **
|count4mhz:3|
|count4mhz:3|lpm_counter:lpm_counter_component|
|count4mhz:3|lpm_counter:lpm_counter_component|f8count:p8c2|
|count4mhz:3|lpm_counter:lpm_counter_component|f8count:p8c1|
|count4mhz:3|lpm_counter:lpm_counter_component|f8count:p8c0|
|count2to0:12|
|count2to0:12|lpm_counter:lpm_counter_component|
|count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|
|7seg:14|
|hourcount:37|
|count6:124|
|count6:124|lpm_counter:lpm_counter_component|
|count6:124|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|
|count6:124|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|
|count6:124|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs|
|count6:124|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs|
|count6:124|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs|
|count6:124|lpm_counter:lpm_counter_component|lpm_constant:scdw|
|count6:124|lpm_counter:lpm_counter_component|cmpconst:89|
|tbhourtqhour:127|
|count24:134|
|select:139|
|digselector:140|
|disp:141|
|main:144|
|subroad:145|
Device-Specific Information: f:\traffic\traffic.rpt
traffic
***** Logic for device 'traffic' compiled without errors.
Device: EP1K30TC144-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
R R R R R R R R R R R R
E E E E E E E E E E E E
S S S S S V S S S S g S S S
E E E E V E C E E E E V r E E E
R R R o o o R o o C o R C c R R R R C e R R R
V V V u u G u V u u C u V G I G l G G V V V V C e V V V
E E E t t N t E t t I t E N d N N k N N E E E E I n E E E
D D D 4 1 D 5 D 3 2 O 0 c f D D p T D 1 D D D a D d D b D O 2 D e D g D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | red3
RESERVED | 8 101 | red8
RESERVED | 9 100 | red2
RESERVED | 10 99 | green8
RESERVED | 11 98 | green3
RESERVED | 12 97 | red7
RESERVED | 13 96 | red4
RESERVED | 14 95 | green7
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | red6
RESERVED | 19 EP1K30TC144-1 90 | green4
RESERVED | 20 89 | green6
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