# Created by Libero Project Manager 8.5.0.34
# Mon Mar 09 09:42:32 2009

# (NEW DESIGN)

# create a new design
new_design -name "my_or" -family "ProASIC3"
set_device -die "A3P030" -package "100 VQFP"


# set default back-annotation base-name
set_defvar "BA_NAME" "my_or_ba"

# set working directory
set_defvar "DESDIR" "E:/work/EasyFPGA030/my_or/designer/impl1"

# set back-annotation output directory
set_defvar "BA_DIR" "E:/work/EasyFPGA030/my_or/designer/impl1"

# enable the export back-annotation netlist
set_defvar "BA_NETLIST_ALSO" "1"

# set EDIF options
set_defvar "EDNINFLAVOR" "GENERIC"

# set HDL options
set_defvar "NETLIST_NAMING_STYLE" "VERILOG"

# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
set_defvar "EXPORT_STATUS_REPORT_FILENAME" "my_or.rpt"

# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
set_defvar "AUDIT_DCF_FILE" "1"
set_defvar "AUDIT_PIN_FILE" "1"
set_defvar "AUDIT_ADL_FILE" "1"

# import of input files
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VERILOG" {../../synthesis/my_or.edn} \
-format "sdc"  {..\..\synthesis\my_or_sdc.sdc}

# save the design database
save_design {my_or.adb}

show_device_selection_wizard