?? spi_master_dddddss.lst
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A51 MACRO ASSEMBLER SPI_MASTER_NO_SS 04/30/2004 16:21:17 PAGE 1
MACRO ASSEMBLER A51 V7.09
OBJECT MODULE PLACED IN spi_master_no_ss.OBJ
ASSEMBLER INVOKED BY: C:\KEIL\C51\BIN\A51.EXE spi_master_no_ss.a51 NOMOD51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;$include (reg_c51.INC)
+1 2 +1 $save
+1 210 +1 $restore
211
0001 212 transmit_completed BIT 20H.1; software flag
0008 213 serial_data DATA 08H
0009 214 data_save DATA 09H
000A 215 data_example DATA 0AH;
216
0000 217 org 000h
0000 020100 218 ljmp begin
219
004B 220 org 4Bh
004B 020134 221 ljmp it_SPI
222
223 ;/**
224 ; * FUNCTION_PURPOSE: This file set up spi in master mode with
225 ; * Fclk Periph/128 as baud rate and without slave select pin
226 ; * FUNCTION_INPUTS: P1.5(MISO) serial input
227 ; * FUNCTION_OUTPUTS: P1.7(MOSI) serial output
228 ; * P1.1
229 ; */
0100 230 org 0100h
0100 231 begin:
232
233 ;init
0100 750A55 234 MOV data_example,#55h; /* data example */
235
0103 43C310 236 ORL SPCON,#10h; /* Master mode */
0106 43C320 237 ORL SPCON,#20h; /* P1.1 is available as standard I/O pin */
0109 43C382 238 ORL SPCON,#82h; /* Fclk Periph/128 */
010C 53C3F7 239 ANL SPCON,#0F7h; /* CPOL=0; transmit mode example */
010F 43C304 240 ORL SPCON,#04h; /* CPHA=1; transmit mode example */
0112 43B104 241 ORL IEN1,#04h; /* enable spi interrupt */
0115 43C340 242 ORL SPCON,#40h; /* run spi */
0118 C201 243 CLR transmit_completed; /* clear software transfert flag */
011A D2AF 244 SETB EA; /* enable interrupts */
245
011C 246 loop:
247
011C B291 248 CPL P1.1; /* P1.1 is available as standard I/O pin */
011E 850AC5 249 MOV SPDAT,data_example; /* send an example data */
0121 3001FD 250 JNB transmit_completed,$; /* wait end of transmition */
0124 C201 251 CLR transmit_completed; /* clear software transfert flag */
252
0126 75C500 253 MOV SPDAT,#00h; /* data is send to generate SCK signal */
0129 3001FD 254 JNB transmit_completed,$; /* wait end of transmition */
012C C201 255 CLR transmit_completed; /* clear software transfert flag */
012E 850809 256 MOV data_save,serial_data; /* save receive data */
257
0131 02011C 258 LJMP loop
259
260
261 ;/**
262 ; * FUNCTION_PURPOSE:interrupt
263 ; * FUNCTION_INPUTS: void
264 ; * FUNCTION_OUTPUTS: transmit_complete is software transfert flag
265 ; */
A51 MACRO ASSEMBLER SPI_MASTER_NO_SS 04/30/2004 16:21:17 PAGE 2
0134 266 it_SPI:; /* interrupt address is 0x004B */
267
0134 AFC4 268 MOV R7,SPSTA;
0136 8FE0 269 MOV ACC,R7
0138 30E705 270 JNB ACC.7,break1;case 0x80:
013B 85C508 271 MOV serial_data,SPDAT; /* read receive data */
013E D201 272 SETB transmit_completed; /* set software flag */
0140 273 break1:
274
0140 30E400 275 JNB ACC.4,break2;case 0x10:
276 ; /* put here for mode fault tasking */
0143 277 break2:;
278
0143 30E600 279 JNB ACC.6,break3;case 0x40:
280 ; /* put here for overrun tasking */
0146 281 break3:;
282
0146 32 283 RETI
284
285 end
A51 MACRO ASSEMBLER SPI_MASTER_NO_SS 04/30/2004 16:21:17 PAGE 3
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
AC . . . . . . . . B ADDR 00D0H.6 A
ACC. . . . . . . . D ADDR 00E0H A
AUXR . . . . . . . D ADDR 008EH A
AUXR1. . . . . . . D ADDR 00A2H A
B. . . . . . . . . D ADDR 00F0H A
BDRCON . . . . . . D ADDR 009BH A
BEGIN. . . . . . . C ADDR 0100H A
BREAK1 . . . . . . C ADDR 0140H A
BREAK2 . . . . . . C ADDR 0143H A
BREAK3 . . . . . . C ADDR 0146H A
BRL. . . . . . . . D ADDR 009AH A
CCAP0H . . . . . . D ADDR 00FAH A
CCAP0L . . . . . . D ADDR 00EAH A
CCAP1H . . . . . . D ADDR 00FBH A
CCAP1L . . . . . . D ADDR 00EBH A
CCAP2H . . . . . . D ADDR 00FCH A
CCAP2L . . . . . . D ADDR 00ECH A
CCAP3H . . . . . . D ADDR 00FDH A
CCAP3L . . . . . . D ADDR 00EDH A
CCAP4H . . . . . . D ADDR 00FEH A
CCAP4L . . . . . . D ADDR 00EEH A
CCAPM0 . . . . . . D ADDR 00DAH A
CCAPM1 . . . . . . D ADDR 00DBH A
CCAPM2 . . . . . . D ADDR 00DCH A
CCAPM3 . . . . . . D ADDR 00DDH A
CCAPM4 . . . . . . D ADDR 00DEH A
CCF0 . . . . . . . B ADDR 00D8H.0 A
CCF1 . . . . . . . B ADDR 00D8H.1 A
CCF2 . . . . . . . B ADDR 00D8H.2 A
CCF3 . . . . . . . B ADDR 00D8H.3 A
CCF4 . . . . . . . B ADDR 00D8H.4 A
CCON . . . . . . . D ADDR 00D8H A
CF . . . . . . . . B ADDR 00D8H.7 A
CH . . . . . . . . D ADDR 00F9H A
CKCON0 . . . . . . D ADDR 008FH A
CKCON1 . . . . . . D ADDR 00AFH A
CKRL . . . . . . . D ADDR 0097H A
CKSEL. . . . . . . D ADDR 0085H A
CL . . . . . . . . D ADDR 00E9H A
CMOD . . . . . . . D ADDR 00D9H A
CP_RL2 . . . . . . B ADDR 00C8H.0 A
CR . . . . . . . . B ADDR 00D8H.6 A
CY . . . . . . . . B ADDR 00D0H.7 A
C_T2 . . . . . . . B ADDR 00C8H.1 A
DATA_EXAMPLE . . . D ADDR 000AH A
DATA_SAVE. . . . . D ADDR 0009H A
DPH. . . . . . . . D ADDR 0083H A
DPL. . . . . . . . D ADDR 0082H A
EA . . . . . . . . B ADDR 00A8H.7 A
EC . . . . . . . . B ADDR 00A8H.6 A
EECON. . . . . . . D ADDR 00D2H A
ES . . . . . . . . B ADDR 00A8H.4 A
ET0. . . . . . . . B ADDR 00A8H.1 A
ET1. . . . . . . . B ADDR 00A8H.3 A
ET2. . . . . . . . B ADDR 00A8H.5 A
EX0. . . . . . . . B ADDR 00A8H.0 A
EX1. . . . . . . . B ADDR 00A8H.2 A
EXEN2. . . . . . . B ADDR 00C8H.3 A
EXF2 . . . . . . . B ADDR 00C8H.6 A
F0 . . . . . . . . B ADDR 00D0H.5 A
A51 MACRO ASSEMBLER SPI_MASTER_NO_SS 04/30/2004 16:21:17 PAGE 4
FCON . . . . . . . D ADDR 00D1H A
IE0. . . . . . . . B ADDR 0088H.1 A
IE1. . . . . . . . B ADDR 0088H.3 A
IEN0 . . . . . . . D ADDR 00A8H A
IEN1 . . . . . . . D ADDR 00B1H A
INT0 . . . . . . . B ADDR 00B0H.2 A
INT1 . . . . . . . B ADDR 00B0H.3 A
IPH0 . . . . . . . D ADDR 00B7H A
IPH1 . . . . . . . D ADDR 00B3H A
IPL0 . . . . . . . D ADDR 00B8H A
IPL1 . . . . . . . D ADDR 00B2H A
IT0. . . . . . . . B ADDR 0088H.0 A
IT1. . . . . . . . B ADDR 0088H.2 A
IT_SPI . . . . . . C ADDR 0134H A
KBE. . . . . . . . D ADDR 009DH A
KBF. . . . . . . . D ADDR 009EH A
KBLS . . . . . . . D ADDR 009CH A
LOOP . . . . . . . C ADDR 011CH A
OSCCON . . . . . . D ADDR 0086H A
OV . . . . . . . . B ADDR 00D0H.2 A
P. . . . . . . . . B ADDR 00D0H.0 A
P0 . . . . . . . . D ADDR 0080H A
P1 . . . . . . . . D ADDR 0090H A
P2 . . . . . . . . D ADDR 00A0H A
P3 . . . . . . . . D ADDR 00B0H A
P4 . . . . . . . . D ADDR 00C0H A
P5 . . . . . . . . D ADDR 00E8H A
PCON . . . . . . . D ADDR 0087H A
PI2. . . . . . . . D ADDR 00F8H A
PI2_1. . . . . . . B ADDR 00F8H.1 A
PI2_O. . . . . . . B ADDR 00F8H.0 A
PPCL . . . . . . . B ADDR 00B8H.6 A
PSL. . . . . . . . B ADDR 00B8H.4 A
PSW. . . . . . . . D ADDR 00D0H A
PT0L . . . . . . . B ADDR 00B8H.1 A
PT1L . . . . . . . B ADDR 00B8H.3 A
PT2L . . . . . . . B ADDR 00B8H.5 A
PX0L . . . . . . . B ADDR 00B8H.0 A
PX1L . . . . . . . B ADDR 00B8H.2 A
RB8. . . . . . . . B ADDR 0098H.2 A
RCAP2H . . . . . . D ADDR 00CBH A
RCAP2L . . . . . . D ADDR 00CAH A
RCLK . . . . . . . B ADDR 00C8H.5 A
RD . . . . . . . . B ADDR 00B0H.7 A
REN. . . . . . . . B ADDR 0098H.4 A
RI . . . . . . . . B ADDR 0098H.0 A
RS0. . . . . . . . B ADDR 00D0H.3 A
RS1. . . . . . . . B ADDR 00D0H.4 A
RXD. . . . . . . . B ADDR 00B0H.0 A
SADDR. . . . . . . D ADDR 00A9H A
SADEN. . . . . . . D ADDR 00B9H A
SBUF . . . . . . . D ADDR 0099H A
SCON . . . . . . . D ADDR 0098H A
SERIAL_DATA. . . . D ADDR 0008H A
SM0. . . . . . . . B ADDR 0098H.7 A
SM1. . . . . . . . B ADDR 0098H.6 A
SM2. . . . . . . . B ADDR 0098H.5 A
SP . . . . . . . . D ADDR 0081H A
SPCON. . . . . . . D ADDR 00C3H A
SPDAT. . . . . . . D ADDR 00C5H A
SPSTA. . . . . . . D ADDR 00C4H A
SSADR. . . . . . . D ADDR 0096H A
SSCON. . . . . . . D ADDR 0093H A
SSCS . . . . . . . D ADDR 0094H A
SSDAT. . . . . . . D ADDR 0095H A
T0 . . . . . . . . B ADDR 00B0H.4 A
A51 MACRO ASSEMBLER SPI_MASTER_NO_SS 04/30/2004 16:21:17 PAGE 5
T1 . . . . . . . . B ADDR 00B0H.5 A
T2CON. . . . . . . D ADDR 00C8H A
T2MOD. . . . . . . D ADDR 00C9H A
TB8. . . . . . . . B ADDR 0098H.3 A
TCLK . . . . . . . B ADDR 00C8H.4 A
TCON . . . . . . . D ADDR 0088H A
TF0. . . . . . . . B ADDR 0088H.5 A
TF1. . . . . . . . B ADDR 0088H.7 A
TF2. . . . . . . . B ADDR 00C8H.7 A
TH0. . . . . . . . D ADDR 008CH A
TH1. . . . . . . . D ADDR 008DH A
TH2. . . . . . . . D ADDR 00CDH A
TI . . . . . . . . B ADDR 0098H.1 A
TL0. . . . . . . . D ADDR 008AH A
TL1. . . . . . . . D ADDR 008BH A
TL2. . . . . . . . D ADDR 00CCH A
TMOD . . . . . . . D ADDR 0089H A
TR0. . . . . . . . B ADDR 0088H.4 A
TR1. . . . . . . . B ADDR 0088H.6 A
TR2. . . . . . . . B ADDR 00C8H.2 A
TRANSMIT_COMPLETED B ADDR 0020H.1 A
TXD. . . . . . . . B ADDR 00B0H.1 A
WDTPRG . . . . . . D ADDR 00A7H A
WDTRST . . . . . . D ADDR 00A6H A
WR . . . . . . . . B ADDR 00B0H.6 A
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)
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