`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:59:48 10/08/08
// Design Name:    
// Module Name:    mux4
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module mux4(m0_in, m1_in, m2_in, m3_in, sel_in, mux4_out);
	 parameter width=8;

    input[width-1:0] m0_in;
    input[width-1:0] m1_in;
    input[width-1:0] m2_in;
    input[width-1:0] m3_in;
    input[1:0] sel_in;
    output[width-1:0] mux4_out;

	 reg[width-1:0] mux4_out;

	 always@(m0_in or m1_in or m2_in or m3_in or sel_in)
	 begin
		 case(sel_in)
		 'b00:mux4_out=m0_in;
		 'b01:mux4_out=m1_in;
		 'b10:mux4_out=m2_in;
		 'b11:mux4_out=m3_in;
		 endcase
	 end

endmodule