Release 7.1.04i Map H.42Xilinx Mapping Report File for Design 'CPU'Design Information------------------Command Line   : C:/Xilinx/bin/nt/map.exe -ise c:\ttttt\ttttt.ise -intstyle ise
-p xcv100-pq240-4 -cm area -pr b -k 4 -c 100 -tx off -o CPU_map.ncd CPU.ngd
CPU.pcf Target Device  : xcv100Target Package : pq240Target Speed   : -4Mapper Version : virtex -- $Revision: 1.26.6.4 $Mapped Date    : Fri Nov 21 11:14:26 2008Design Summary--------------Number of errors:      0Number of warnings:    4Logic Utilization:  Total Number Slice Registers:     174 out of  2,400    7%    Number used as Flip Flops:                    134    Number used as Latches:                        40  Number of 4 input LUTs:           788 out of  2,400   32%Logic Distribution:    Number of occupied Slices:                         465 out of  1,200   38%    Number of Slices containing only related logic:    465 out of    465  100%    Number of Slices containing unrelated logic:         0 out of    465    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          808 out of  2,400   33%      Number used as logic:                       788      Number used as a route-thru:                 20   Number of bonded IOBs:            20 out of    166   12%   Number of GCLKs:                   3 out of      4   75%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  6,921Additional JTAG gate count for IOBs:  1,008Peak Memory Usage:  100 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.   	MUL/MUL__n0002<7>cy   	MUL/MUL__n0002<8>cyWARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.   	MUL/MUL__n0003<5>cy   	MUL/MUL__n0003<6>cyWARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.   	MUL/MUL__n0005<3>cy   	MUL/MUL__n0005<4>cyWARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.   	MUL/MUL__n0006<1>cy   	MUL/MUL__n0006<2>cySection 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   3 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKLUT1 		N1_rtGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || CS                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || READ                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || WRITE                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || address<7>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || data<0>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<1>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<2>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<3>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<4>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<5>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<6>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || data<7>                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || rst                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 21Number of Equivalent Gates for Design = 6,921Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 3Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 39IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 20XORs = 103CARRY_INITs = 62CARRY_SKIPs = 0CARRY_MUXes = 112Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 24MUXF5s + MUXF6s = 724 input LUTs used as Route-Thrus = 204 input LUTs = 788Slice Latches not driven by LUTs = 13Slice Latches = 40Slice Flip Flops not driven by LUTs = 26Slice Flip Flops = 134Slices = 465F6 Muxes = 12F5 Muxes = 60Number of LUT signals with 4 loads = 6Number of LUT signals with 3 loads = 29Number of LUT signals with 2 loads = 342Number of LUT signals with 1 load = 336NGM Average fanout of LUT = 2.72NGM Maximum fanout of LUT = 42NGM Average fanin for LUT = 3.5952Number of LUT symbols = 788