Release 7.1.04i par H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.305COMPUTER13::  Fri Nov 21 11:14:30 2008par -w -intstyle ise -ol std -t 1 CPU_map.ncd CPU.ncd CPU.pcf Constraints file: CPU.pcf.Loading device for application Rf_Device from file 'v100.nph' in environment
C:/Xilinx.   "CPU" is an NCD, version 3.1, device xcv100, package pq240, speed -4Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 125.000
Celsius)Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)Device speed data version:  "FINAL 1.123 2005-01-22".Device Utilization Summary:   Number of GCLKs                     3 out of 4      75%   Number of External GCLKIOBs         1 out of 4      25%      Number of LOCed GCLKIOBs         1 out of 1     100%   Number of External IOBs            20 out of 166    12%      Number of LOCed IOBs            20 out of 20    100%   Number of SLICEs                  465 out of 1200   38%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Starting PlacerPhase 1.1Phase 1.1 (Checksum:98a3df) REAL time: 0 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs Phase 3.23Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 0 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs Phase 6.8...............Phase 6.8 (Checksum:a51edb) REAL time: 1 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs Writing design to file CPU.ncdTotal REAL time to Placer completion: 1 secs Total CPU time to Placer completion: 0 secs Starting RouterPhase 1: 3381 unrouted;       REAL time: 1 secs Phase 2: 3278 unrouted;       REAL time: 1 secs Phase 3: 1095 unrouted;       REAL time: 1 secs Phase 4: 0 unrouted;       REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|               DIVLE |      GCLKBUF1| No   |   21 |  0.077     |  0.493      |+---------------------+--------------+------+------+------------+-------------+|           clk_BUFGP |      GCLKBUF3| No   |   73 |  0.073     |  0.523      |+---------------------+--------------+------+------+------------+-------------+|               MULLE |      GCLKBUF0| No   |   17 |  0.046     |  0.492      |+---------------------+--------------+------+------+------------+-------------+INFO:Par:340 -    The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage:  71 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file CPU.ncdPAR done!