{    MakeSR();    if (!regs.s) {		regs.usp = m68k_areg(regs, 7);		m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;		regs.s = 1;    }    if (nr == 2 || nr == 3) {		int i;		/* @@@ this is probably wrong (?) */		for (i = 0 ; i < 12 ; i++) {			m68k_areg(regs, 7) -= 2;			cpu_writemem24_word (m68k_areg(regs, 7), 0);		}		m68k_areg(regs, 7) -= 2;		cpu_writemem24_word(m68k_areg(regs, 7), 0xa000 + nr * 4);	} else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {		m68k_areg(regs, 7) -= 4;		cpu_writemem24_dword (m68k_areg(regs, 7), oldpc);		m68k_areg(regs, 7) -= 2;		cpu_writemem24_word (m68k_areg(regs, 7), 0x2000 + nr * 4);	} else if (regs.m && nr >= 24 && nr < 32) {		m68k_areg(regs, 7) -= 2;		cpu_writemem24_word (m68k_areg(regs, 7), nr * 4);		m68k_areg(regs, 7) -= 4;		cpu_writemem24_dword (m68k_areg(regs, 7), m68k_getpc ());		m68k_areg(regs, 7) -= 2;		cpu_writemem24_word (m68k_areg(regs, 7), regs.sr);		regs.sr |= (1 << 13);		regs.msp = m68k_areg(regs, 7);		m68k_areg(regs, 7) = regs.isp;		m68k_areg(regs, 7) -= 2;		cpu_writemem24_word (m68k_areg(regs, 7), 0x1000 + nr * 4);	} else {		m68k_areg(regs, 7) -= 2;		cpu_writemem24_word (m68k_areg(regs, 7), nr * 4);	}    m68k_areg(regs, 7) -= 4;    cpu_writemem24_dword (m68k_areg(regs, 7), m68k_getpc ());	//kludge_me_do:    m68k_areg(regs, 7) -= 2;    cpu_writemem24_word (m68k_areg(regs, 7), regs.sr);    m68k_setpc (cpu_readmem24_dword (regs.vbr + 4*nr));    regs.t1 = regs.t0 = regs.m = 0;}static int caar, cacr;int m68k_move2c (int regno, UINT32 *regp){	switch (regno) {	case 0: regs.sfc = *regp & 7; break;	case 1: regs.dfc = *regp & 7; break;	case 2: cacr = *regp & 0x3; break;	/* ignore C and CE */	case 0x800: regs.usp = *regp; break;	case 0x801: regs.vbr = *regp; break;	case 0x802: caar = *regp &0xfc; break;	case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;	case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;	default:		op_illg (0x4E7B);		return 0;	}    return 1;}int m68k_movec2 (int regno, UINT32 *regp){	switch (regno) {	case 0: *regp = regs.sfc; break;	case 1: *regp = regs.dfc; break;	case 2: *regp = cacr; break;	case 0x800: *regp = regs.usp; break;	case 0x801: *regp = regs.vbr; break;	case 0x802: *regp = caar; break;	case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;	case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;	default:		op_illg (0x4E7A);		return 0;	}    return 1;}static DEF_INLINE intdiv_unsigned(UINT32 src_hi, UINT32 src_lo, UINT32 div, UINT32 *quot, UINT32 *rem){	UINT32 q = 0, cbit = 0;	int i;		if (div <= src_hi) {		return 1;	}	for (i = 0 ; i < 32 ; i++) {		cbit = src_hi & 0x80000000ul;		src_hi <<= 1;		if (src_lo & 0x80000000ul) src_hi++;		src_lo <<= 1;		q = q << 1;		if (cbit || div <= src_hi) {			q |= 1;			src_hi -= div;		}	}	*quot = q;	*rem = src_hi;	return 0;}void m68k_divl (UINT32 opcode, UINT32 src, UINT16 extra, CPTR oldpc){	(void)(opcode);    if (src == 0) {		Exception (5, oldpc);		return;    }    if (extra & 0x800) {		/* signed variant */		INT64 a = (INT64)(INT32)m68k_dreg(regs, (extra >> 12) & 7);		INT64 quot, rem;				if (extra & 0x400) {			a &= 0xffffffffu;			a |= (INT64)m68k_dreg(regs, extra & 7) << 32;		}		rem = a % (INT64)(INT32)src;		quot = a / (INT64)(INT32)src;		if ((quot & (UINT64)(0xffffffff80000000)) != 0			&& (quot & (UINT64)(0xffffffff80000000)) != (UINT64)(0xffffffff80000000))		{			SET_VFLG (1);			SET_NFLG (1);			SET_CFLG (0);		} else {			if (((INT32)rem < 0) != ((INT64)a < 0)) rem = -rem;			SET_VFLG (0);			SET_CFLG (0);			SET_ZFLG (((INT32)quot) == 0);			SET_NFLG (((INT32)quot) < 0);			m68k_dreg(regs, extra & 7) = rem;			m68k_dreg(regs, (extra >> 12) & 7) = quot;		}    } else {		/* unsigned */		UINT64 a = (UINT64)(INT32)m68k_dreg(regs, (extra >> 12) & 7);		UINT64 quot, rem;				if (extra & 0x400) {			a &= 0xffffffffu;			a |= (UINT64)m68k_dreg(regs, extra & 7) << 32;		}		rem = a % (UINT64)src;		quot = a / (UINT64)src;		if (quot > 0xffffffffu) {			SET_VFLG (1);			SET_NFLG (1);			SET_CFLG (0);		} else {			SET_VFLG (0);			SET_CFLG (0);			SET_ZFLG (((INT32)quot) == 0);			SET_NFLG (((INT32)quot) < 0);			m68k_dreg(regs, extra & 7) = rem;			m68k_dreg(regs, (extra >> 12) & 7) = quot;		}    }}static DEF_INLINE voidmul_unsigned(UINT32 src1, UINT32 src2, UINT32 *dst_hi, UINT32 *dst_lo){	UINT32 r0 = (src1 & 0xffff) * (src2 & 0xffff);	UINT32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);	UINT32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);	UINT32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);	UINT32 lo;		lo = r0 + ((r1 << 16) & 0xffff0000ul);	if (lo < r0) r3++;	r0 = lo;	lo = r0 + ((r2 << 16) & 0xffff0000ul);	if (lo < r0) r3++;	r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);	*dst_lo = lo;	*dst_hi = r3;}void m68k_mull (UINT32 opcode, UINT32 src, UINT16 extra){	(void)(opcode);    if (extra & 0x800) {		/* signed variant */		UINT64 a = (INT64)(INT32)m68k_dreg(regs, (extra >> 12) & 7);				a *= (INT64)(INT32)src;		SET_VFLG (0);		SET_CFLG (0);		SET_ZFLG (a == 0);		SET_NFLG (a < 0);		if (extra & 0x400)			m68k_dreg(regs, extra & 7) = a >> 32;		else if ((a & (UINT64)(0xffffffff80000000)) != 0			&& (a & (UINT64)(0xffffffff80000000)) != (UINT64)(0xffffffff80000000))		{			SET_VFLG (1);		}		m68k_dreg(regs, (extra >> 12) & 7) = (UINT32)a;    } else {		/* unsigned */		UINT64 a = (UINT64)(UINT32)m68k_dreg(regs, (extra >> 12) & 7);				a *= (UINT64)src;		SET_VFLG (0);		SET_CFLG (0);		SET_ZFLG (a == 0);		SET_NFLG (((UINT64)a) < 0);		if (extra & 0x400)			m68k_dreg(regs, extra & 7) = a >> 32;		else if ((a & (UINT64)(0xffffffff00000000)) != 0) {			SET_VFLG (1);		}		m68k_dreg(regs, (extra >> 12) & 7) = (UINT32)a;    }}static char* ccnames[] ={ "T ","F ","HI","LS","CC","CS","NE","EQ","VC","VS","PL","MI","GE","LT","GT","LE" };void Reset68020 (void){    m68k_areg (regs, 7) = cpu_readmem24_dword(0);    m68k_setpc (cpu_readmem24_dword(4));    regs.s = 1;    regs.m = 0;    regs.stopped = 0;    regs.t1 = 0;    regs.t0 = 0;    SET_ZFLG (0);    SET_XFLG (0);    SET_CFLG (0);    SET_VFLG (0);    SET_NFLG (0);    regs.intmask = 7;    regs.vbr = regs.sfc = regs.dfc = 0;	regs.sr=0x2700;	MakeFromSR();}unsigned long op_illg (UINT32 opcode){	(void)(opcode);        Exception (4,0);    return 4;}static int n_insns = 0, n_spcinsns = 0;static CPTR last_trace_ad = 0;void m68k_disasm (CPTR addr, CPTR *nextpc, int cnt, output_func_ptr debug_out){    CPTR newpc = 0;    m68kpc_offset = addr - m68k_getpc ();    while (cnt-- > 0) {		char instrname[20],*ccpt;		int opwords;		UINT32 opcode;		struct mnemolookup *lookup;		struct instr *dp;		(*debug_out) ("%08lx: ", m68k_getpc () + m68kpc_offset);		for (opwords = 0; opwords < 5; opwords++){			(*debug_out) ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));		}		opcode = get_iword_1 (m68kpc_offset);		m68kpc_offset += 2;		if (cpufunctbl[opcode] == op_illg_1) {			opcode = 0x4AFC;		}		dp = table68k + opcode;		for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)			;				strcpy (instrname, lookup->name);		ccpt = strstr (instrname, "cc");		if (ccpt != 0) {			strncpy (ccpt, ccnames[dp->cc], 2);		}		(*debug_out) ("%s", instrname);		switch (dp->size){		case sz_byte: (*debug_out) (".B "); break;		case sz_word: (*debug_out) (".W "); break;		case sz_long: (*debug_out) (".L "); break;		default: (*debug_out) ("   "); break;		}				if (dp->suse) {			newpc = m68k_getpc () + m68kpc_offset;			newpc += ShowEA (dp->sreg, dp->smode, dp->size, 0, debug_out);		}		if (dp->suse && dp->duse)			(*debug_out) (",");		if (dp->duse) {			newpc = m68k_getpc () + m68kpc_offset;			newpc += ShowEA (dp->dreg, dp->dmode, dp->size, 0, debug_out);		}		if (ccpt != 0) {			if (cctrue(dp->cc))				(*debug_out) (" == %08lx (TRUE)", newpc);			else				(*debug_out) (" == %08lx (FALSE)", newpc);		} else if ((opcode & 0xff00) == 0x6100) /* BSR */			(*debug_out) (" == %08lx", newpc);		(*debug_out) ("\n");    }    if (nextpc)		*nextpc = m68k_getpc () + m68kpc_offset;}void Execute68020(int c){	UINT32 opcode;	cycles = (c>>4);    while ( cycles )	{		opcode = get_iword (0);		cycles -= (*cpufunctbl[opcode])(opcode);		opcode = get_iword (0);		cycles -= (*cpufunctbl[opcode])(opcode);		opcode = get_iword (0);		cycles -= (*cpufunctbl[opcode])(opcode);		opcode = get_iword (0);		cycles -= (*cpufunctbl[opcode])(opcode);	}}void Interrupt68020(int level){	MakeSR();	if(level>=((regs.sr&0xf00)>>8)) Exception(level+24,regs.pc);}void Stop68020(void){   cycles=0;}