#include "raine.h"#include "newmem.h"#include "readcpu.h"int nr_cpuop_funcs;#define CPU_EMU_SIZE 0struct mnemolookup lookuptab[] ={    { i_ILLG, "ILLEGAL" },    { i_OR, "OR" },    { i_CHK, "CHK" },    { i_CHK2, "CHK2" },    { i_AND, "AND" },    { i_EOR, "EOR" },    { i_ORSR, "ORSR" },    { i_ANDSR, "ANDSR" },    { i_EORSR, "EORSR" },    { i_SUB, "SUB" },    { i_SUBA, "SUBA" },    { i_SUBX, "SUBX" },    { i_SBCD, "SBCD" },    { i_ADD, "ADD" },    { i_ADDA, "ADDA" },    { i_ADDX, "ADDX" },    { i_ABCD, "ABCD" },    { i_NEG, "NEG" },    { i_NEGX, "NEGX" },    { i_NBCD, "NBCD" },    { i_CLR, "CLR" },    { i_NOT, "NOT" },    { i_TST, "TST" },    { i_BTST, "BTST" },    { i_BCHG, "BCHG" },    { i_BCLR, "BCLR" },    { i_BSET, "BSET" },    { i_CMP, "CMP" },    { i_CMPM, "CMPM" },    { i_CMPA, "CMPA" },    { i_MVPRM, "MVPRM" },    { i_MVPMR, "MVPMR" },    { i_MOVE, "MOVE" },    { i_MOVEA, "MOVEA" },    { i_MVSR2, "MVSR2" },    { i_MV2SR, "MV2SR" },    { i_SWAP, "SWAP" },    { i_EXG, "EXG" },    { i_EXT, "EXT" },    { i_MVMEL, "MVMEL" },    { i_MVMLE, "MVMLE" },    { i_TRAP, "TRAP" },    { i_MVR2USP, "MVR2USP" },    { i_MVUSP2R, "MVUSP2R" },    { i_NOP, "NOP" },    { i_RESET, "RESET" },    { i_RTE, "RTE" },    { i_RTD, "RTD" },    { i_LINK, "LINK" },    { i_UNLK, "UNLK" },    { i_RTS, "RTS" },    { i_STOP, "STOP" },    { i_TRAPV, "TRAPV" },    { i_RTR, "RTR" },    { i_JSR, "JSR" },    { i_JMP, "JMP" },    { i_BSR, "BSR" },    { i_Bcc, "Bcc" },    { i_LEA, "LEA" },    { i_PEA, "PEA" },    { i_DBcc, "DBcc" },    { i_Scc, "Scc" },    { i_DIVU, "DIVU" },    { i_DIVS, "DIVS" },    { i_MULU, "MULU" },    { i_MULS, "MULS" },    { i_ASR, "ASR" },    { i_ASL, "ASL" },    { i_LSR, "LSR" },    { i_LSL, "LSL" },    { i_ROL, "ROL" },    { i_ROR, "ROR" },    { i_ROXL, "ROXL" },    { i_ROXR, "ROXR" },    { i_ASRW, "ASRW" },    { i_ASLW, "ASLW" },    { i_LSRW, "LSRW" },    { i_LSLW, "LSLW" },    { i_ROLW, "ROLW" },    { i_RORW, "RORW" },    { i_ROXLW, "ROXLW" },    { i_ROXRW, "ROXRW" },	    { i_MOVE2C, "MOVE2C" },    { i_MOVEC2, "MOVEC2" },    { i_CAS, "CAS" },    { i_CAS2, "CAS2" },    { i_MULL, "MULL" },    { i_DIVL, "DIVL" },    { i_BFTST, "BFTST" },    { i_BFEXTU, "BFEXTU" },    { i_BFCHG, "BFCHG" },    { i_BFEXTS, "BFEXTS" },    { i_BFCLR, "BFCLR" },    { i_BFFFO, "BFFFO" },    { i_BFSET, "BFSET" },    { i_BFINS, "BFINS" },    { i_PACK, "PACK" },    { i_UNPK, "UNPK" },    { i_TAS, "TAS" },    { i_BKPT, "BKPT" },    { i_CALLM, "CALLM" },    { i_RTM, "RTM" },    { i_TRAPcc, "TRAPcc" },    { i_MOVES, "MOVES" },    { i_FPP, "FPP" },    { i_FDBcc, "FDBcc" },    { i_FScc, "FScc" },    { i_FTRAPcc, "FTRAPcc" },    { i_FBcc, "FBcc" },    { i_FBcc, "FBcc" },    { i_FSAVE, "FSAVE" },    { i_FRESTORE, "FRESTORE" },    { i_MMUOP, "MMUOP" },    { i_ILLG, "" },};struct instr *table68k;static int u020_strncmp(const char *a, const char *b, int len){	int i;	for(i=0;i<len;i++){		if(a[i] != b[i])			return 1;	}	return 0;}static void u020_abort(void){}static int u020_isspace(char a){	if((a == 0x20) || (a == 0x0D) || (a == 0x0A) || (a == 0x09))		return 1;	else		return 0;}static DEF_INLINE amodes mode_from_str (const char *str){    if (! u020_strncmp (str, "Dreg", 4)) return Dreg;    if (! u020_strncmp (str, "Areg", 4)) return Areg;    if (! u020_strncmp (str, "Aind", 4)) return Aind;    if (! u020_strncmp (str, "Apdi", 4)) return Apdi;    if (! u020_strncmp (str, "Aipi", 4)) return Aipi;    if (! u020_strncmp (str, "Ad16", 4)) return Ad16;    if (! u020_strncmp (str, "Ad8r", 4)) return Ad8r;    if (! u020_strncmp (str, "absw", 4)) return absw;    if (! u020_strncmp (str, "absl", 4)) return absl;    if (! u020_strncmp (str, "PC16", 4)) return PC16;    if (! u020_strncmp (str, "PC8r", 4)) return PC8r;    if (! u020_strncmp (str, "Immd", 4)) return imm;    u020_abort ();    return(0);}static DEF_INLINE amodes mode_from_mr (int mode, int reg){    switch (mode) {	case 0: return Dreg;	case 1: return Areg;	case 2: return Aind;	case 3: return Aipi;	case 4: return Apdi;	case 5: return Ad16;	case 6: return Ad8r;	case 7:		switch (reg) {		case 0: return absw;		case 1: return absl;		case 2: return PC16;		case 3: return PC8r;		case 4: return imm;		case 5:		case 6:		case 7: return am_illg;		}    }    u020_abort ();    return(0);}static void build_insn (int insn){    int find = -1;    int variants;    struct instr_def id;    const char *opcstr;    int i;	    int flaglive = 0, flagdead = 0;	    id = defs68k[insn];	    for (i = 0; i < 5; i++) {		switch (id.flaginfo[i].flagset){		case fa_unset: break;		case fa_isjmp: break;		case fa_zero: flagdead |= 1 << i; break;		case fa_one: flagdead |= 1 << i; break;		case fa_dontcare: flagdead |= 1 << i; break;		case fa_unknown: flagdead = -1; goto out1;		case fa_set: flagdead |= 1 << i; break;		}    }	out1:    for (i = 0; i < 5; i++) {		switch (id.flaginfo[i].flaguse) {		case fu_unused: break;		case fu_isjmp: flaglive |= 1 << i; break;		case fu_maybecc: flaglive |= 1 << i; break;		case fu_unknown: flaglive = -1; goto out2;		case fu_used: flaglive |= 1 << i; break;		}    }out2:	    opcstr = id.opcstr;    for (variants = 0; variants < (1 << id.n_variable); variants++) {		int bitcnt[lastbit];		int bitval[lastbit];		int bitpos[lastbit];		int i;		UINT16 opc = id.bits;		UINT16 msk, vmsk;		int pos = 0;		int mnp = 0;		int bitno = 0;		char mnemonic[10];				wordsizes sz = sz_long;		int srcgather = 0, dstgather = 0;		int usesrc = 0, usedst = 0;		int srctype = 0;		int srcpos = -1, dstpos = -1;				amodes srcmode = am_unknown, destmode = am_unknown;		int srcreg = -1, destreg = -1;				for (i = 0; i < lastbit; i++)			bitcnt[i] = bitval[i] = 0;				vmsk = 1 << id.n_variable;				for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) {			if (!(msk & id.mask)) {				int currbit = id.bitpos[bitno++];				int bit_set;				vmsk >>= 1;				bit_set = variants & vmsk ? 1 : 0;				if (bit_set)					opc |= msk;				bitpos[currbit] = 15 - i;				bitcnt[currbit]++;				bitval[currbit] <<= 1;				bitval[currbit] |= bit_set;			}		}				if (bitval[bitj] == 0) bitval[bitj] = 8;		/* first check whether this one does not match after all */		if (bitval[bitz] == 3 || bitval[bitC] == 1)			continue;		if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))			continue;				/* bitI and bitC get copied to biti and bitc */		if (bitcnt[bitI]) {			bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];		}		if (bitcnt[bitC])			bitval[bitc] = bitval[bitC];				pos = 0;		while (opcstr[pos] && !u020_isspace(opcstr[pos])) {			if (opcstr[pos] == '.') {				pos++;				switch (opcstr[pos]) {									case 'B': sz = sz_byte; break;				case 'W': sz = sz_word; break;				case 'L': sz = sz_long; break;				case 'z':					switch (bitval[bitz]) {					case 0: sz = sz_byte; break;					case 1: sz = sz_word; break;					case 2: sz = sz_long; break;					default: u020_abort();					}					break;					default: u020_abort();				}			} else {				mnemonic[mnp] = opcstr[pos];				if (mnemonic[mnp] == 'f') {					find = -1;					switch (bitval[bitf]) {					case 0: mnemonic[mnp] = 'R'; break;					case 1: mnemonic[mnp] = 'L'; break;					default: u020_abort();					}				}				mnp++;			}			pos++;		}		mnemonic[mnp] = 0;				/* now, we have read the mnemonic and the size */		while (opcstr[pos] && u020_isspace(opcstr[pos]))			pos++;				/* A goto a day keeps the D******a away. */		if (opcstr[pos] == 0)			goto endofline;				/* parse the source address */		usesrc = 1;		switch (opcstr[pos++]) {		case 'D':			srcmode = Dreg;			switch (opcstr[pos++]) {			case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;			case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;			default: u020_abort();			}						break;			case 'A':				srcmode = Areg;				switch (opcstr[pos++]) {				case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;				case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;				default: u020_abort();				}				switch (opcstr[pos]) {				case 'p': srcmode = Apdi; pos++; break;				case 'P': srcmode = Aipi; pos++; break;				}				break;				case '#':					switch (opcstr[pos++]) {					case 'z': srcmode = imm; break;					case '0': srcmode = imm0; break;					case '1': srcmode = imm1; break;					case '2': srcmode = imm2; break;					case 'i': srcmode = immi; srcreg = (INT32)(INT8)bitval[biti];						if (CPU_EMU_SIZE < 4) {							/* Used for branch instructions */							srctype = 1;							srcgather = 1;							srcpos = bitpos[biti];						}						break;					case 'j': srcmode = immi; srcreg = bitval[bitj];						if (CPU_EMU_SIZE < 3) {							/* 1..8 for ADDQ/SUBQ and rotshi insns */							srcgather = 1;							srctype = 3;							srcpos = bitpos[bitj];						}						break;					case 'J': srcmode = immi; srcreg = bitval[bitJ];						if (CPU_EMU_SIZE < 5) {							/* 0..15 */							srcgather = 1;							srctype = 2;							srcpos = bitpos[bitJ];						}						break;					case 'k': srcmode = immi; srcreg = bitval[bitk];						if (CPU_EMU_SIZE < 3) {							srcgather = 1;							srctype = 4;							srcpos = bitpos[bitk];						}						break;					case 'K': srcmode = immi; srcreg = bitval[bitK];						if (CPU_EMU_SIZE < 5) {							/* 0..15 */							srcgather = 1;							srctype = 5;							srcpos = bitpos[bitK];						}						break;					default: u020_abort();					}					break;					case 'd':						srcreg = bitval[bitD];						srcmode = mode_from_mr(bitval[bitd],bitval[bitD]);						if (srcmode == am_illg)