?? f3system.c
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/******************************************************************************//* *//* TAITO F3-SYSTEM SUPPORT *//* *//******************************************************************************/#include "gameinc.h"#include "f3system.h"#include "savegame.h"#include "debug.h"#include "mame/handlers.h"#include "sasound.h" // Including this one in f3... !!!//#define DUMP 1char f3_shared_ram[0x10000];struct INPUT_INFO f3_system_inputs[] ={ { KB_DEF_COIN1, MSG_COIN1, 0x069001, 0x10, BIT_ACTIVE_0 }, { KB_DEF_COIN2, MSG_COIN2, 0x069001, 0x20, BIT_ACTIVE_0 }, { KB_DEF_TILT, MSG_TILT, 0x069002, 0x01, BIT_ACTIVE_0 }, { KB_DEF_SERVICE, MSG_SERVICE, 0x069002, 0x0E, BIT_ACTIVE_0 }, { KB_DEF_TEST, MSG_TEST, 0x069001, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_START, MSG_P1_START, 0x069002, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P1_UP, MSG_P1_UP, 0x069007, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_DOWN, MSG_P1_DOWN, 0x069007, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_LEFT, MSG_P1_LEFT, 0x069007, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P1_RIGHT, MSG_P1_RIGHT, 0x069007, 0x08, BIT_ACTIVE_0 }, { KB_DEF_P1_B1, MSG_P1_B1, 0x069003, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_B2, MSG_P1_B2, 0x069003, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_B3, MSG_P1_B3, 0x069003, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P2_START, MSG_P2_START, 0x069002, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_UP, MSG_P2_UP, 0x069007, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P2_DOWN, MSG_P2_DOWN, 0x069007, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_LEFT, MSG_P2_LEFT, 0x069007, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P2_RIGHT, MSG_P2_RIGHT, 0x069007, 0x80, BIT_ACTIVE_0 }, { KB_DEF_P2_B1, MSG_P2_B1, 0x069003, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P2_B2, MSG_P2_B2, 0x069003, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_B3, MSG_P2_B3, 0x069003, 0x40, BIT_ACTIVE_0 }, { 0, NULL, 0, 0, 0 },};struct INPUT_INFO f3_system_inputs_6_button[] ={ { KB_DEF_COIN1, MSG_COIN1, 0x069001, 0x10, BIT_ACTIVE_0 }, { KB_DEF_COIN2, MSG_COIN2, 0x069001, 0x20, BIT_ACTIVE_0 }, { KB_DEF_TILT, MSG_TILT, 0x069002, 0x01, BIT_ACTIVE_0 }, { KB_DEF_SERVICE, MSG_SERVICE, 0x069002, 0x0E, BIT_ACTIVE_0 }, { KB_DEF_TEST, MSG_TEST, 0x069001, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_START, MSG_P1_START, 0x069002, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P1_UP, MSG_P1_UP, 0x069007, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_DOWN, MSG_P1_DOWN, 0x069007, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_LEFT, MSG_P1_LEFT, 0x069007, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P1_RIGHT, MSG_P1_RIGHT, 0x069007, 0x08, BIT_ACTIVE_0 }, { KB_DEF_P1_B1, MSG_P1_B1, 0x069003, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_B2, MSG_P1_B2, 0x069003, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_B3, MSG_P1_B3, 0x069003, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P1_B4, MSG_P1_B4, 0x069017, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_B5, MSG_P1_B5, 0x069017, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_B6, MSG_P1_B6, 0x069017, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P2_START, MSG_P2_START, 0x069002, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_UP, MSG_P2_UP, 0x069007, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P2_DOWN, MSG_P2_DOWN, 0x069007, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_LEFT, MSG_P2_LEFT, 0x069007, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P2_RIGHT, MSG_P2_RIGHT, 0x069007, 0x80, BIT_ACTIVE_0 }, { KB_DEF_P2_B1, MSG_P2_B1, 0x069003, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P2_B2, MSG_P2_B2, 0x069003, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_B3, MSG_P2_B3, 0x069003, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P2_B4, MSG_P2_B4, 0x069012, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P2_B5, MSG_P2_B5, 0x069012, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P2_B6, MSG_P2_B6, 0x069012, 0x04, BIT_ACTIVE_0 }, { 0, NULL, 0, 0, 0 },};struct INPUT_INFO f3_system_inputs_4_player[] ={ { KB_DEF_COIN1, MSG_COIN1, 0x069001, 0x10, BIT_ACTIVE_0 }, { KB_DEF_COIN2, MSG_COIN2, 0x069001, 0x20, BIT_ACTIVE_0 }, { KB_DEF_COIN3, MSG_COIN3, 0x069001, 0x40, BIT_ACTIVE_0 }, { KB_DEF_COIN4, MSG_COIN4, 0x069001, 0x80, BIT_ACTIVE_0 }, { KB_DEF_TILT, MSG_TILT, 0x069002, 0x01, BIT_ACTIVE_0 }, { KB_DEF_SERVICE, MSG_SERVICE, 0x069002, 0x0E, BIT_ACTIVE_0 }, { KB_DEF_TEST, MSG_TEST, 0x069001, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_START, MSG_P1_START, 0x069002, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P1_UP, MSG_P1_UP, 0x069007, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_DOWN, MSG_P1_DOWN, 0x069007, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_LEFT, MSG_P1_LEFT, 0x069007, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P1_RIGHT, MSG_P1_RIGHT, 0x069007, 0x08, BIT_ACTIVE_0 }, { KB_DEF_P1_B1, MSG_P1_B1, 0x069003, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P1_B2, MSG_P1_B2, 0x069003, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P1_B3, MSG_P1_B3, 0x069003, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P2_START, MSG_P2_START, 0x069002, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_UP, MSG_P2_UP, 0x069007, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P2_DOWN, MSG_P2_DOWN, 0x069007, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_LEFT, MSG_P2_LEFT, 0x069007, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P2_RIGHT, MSG_P2_RIGHT, 0x069007, 0x80, BIT_ACTIVE_0 }, { KB_DEF_P2_B1, MSG_P2_B1, 0x069003, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P2_B2, MSG_P2_B2, 0x069003, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P2_B3, MSG_P2_B3, 0x069003, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P3_START, MSG_P3_START, 0x069002, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P3_UP, MSG_P3_UP, 0x069017, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P3_DOWN, MSG_P3_DOWN, 0x069017, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P3_LEFT, MSG_P3_LEFT, 0x069017, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P3_RIGHT, MSG_P3_RIGHT, 0x069017, 0x08, BIT_ACTIVE_0 }, { KB_DEF_P3_B1, MSG_P3_B1, 0x069012, 0x01, BIT_ACTIVE_0 }, { KB_DEF_P3_B2, MSG_P3_B2, 0x069012, 0x02, BIT_ACTIVE_0 }, { KB_DEF_P3_B3, MSG_P3_B3, 0x069012, 0x04, BIT_ACTIVE_0 }, { KB_DEF_P4_START, MSG_P4_START, 0x069002, 0x80, BIT_ACTIVE_0 }, { KB_DEF_P4_UP, MSG_P4_UP, 0x069017, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P4_DOWN, MSG_P4_DOWN, 0x069017, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P4_LEFT, MSG_P4_LEFT, 0x069017, 0x40, BIT_ACTIVE_0 }, { KB_DEF_P4_RIGHT, MSG_P4_RIGHT, 0x069017, 0x80, BIT_ACTIVE_0 }, { KB_DEF_P4_B1, MSG_P4_B1, 0x069012, 0x10, BIT_ACTIVE_0 }, { KB_DEF_P4_B2, MSG_P4_B2, 0x069012, 0x20, BIT_ACTIVE_0 }, { KB_DEF_P4_B3, MSG_P4_B3, 0x069012, 0x40, BIT_ACTIVE_0 }, { 0, NULL, 0, 0, 0 },};static int es_tmp=1,timer_mode;static int counter,vector_reg,imr_status,m68681_imr;static data16_t es5510_dsp_ram[0x200];static data32_t es5510_gpr[0xc0];static data32_t es5510_gpr_latch;static void *timer_68681=NULL;int int7_active = 0; // Must take this into account when executing the frame...int f3_cycles_68000,f3_slices;struct ES5505interface es5505_interface = { 1, /* total number of chips */ { 16000000 }, /* freq */ { 0 }, /* Bank 0: Unused by F3 games? */ { 0 }, /* Bank 1: All games seem to use this */ { YM3012_VOL(255,MIXER_PAN_LEFT,255,MIXER_PAN_RIGHT) }, /* master volume */ { 0 } /* irq callback */};struct SOUND_INFO f3_sound[] ={ { SOUND_ES5505, &es5505_interface, }, { 0, NULL, },};int max_banks_this_game; //=memory_region_length(REGION_SOUND1)/0x200000;UINT8 *M68000ROM, *M68000RAM; // sound 68000 memory...// For the timer, might be usefull...#define M68000_CLOCK 16000000#define M68681_CLOCK 2000000 /* Actually X1, not the main clock */// Byte Expand : 8 bits to 16 bits...void load_be(char *name, UINT8 *ROM, int size){ UINT8 *TMP; int n; if(!(TMP=AllocateMem(size))) return; if(!load_rom(name, TMP, size)) return; for (n=0; n<size; n++) WriteWord68k(ROM+(n<<1),TMP[n]); FreeMem(TMP);}READ16_HANDLER(f3_68000_share_rw){ //fprintf(stderr,"_rw\n"); //exit(1); fprintf(stderr,"rw\n"); return ReadWord68k(f3_shared_ram+(offset & 0xfff));}INLINE int convert_offset(int offset) { offset >>=1; offset &= 0xfff; return offset;}READ_HANDLER( f3_68000_share_rb ) { int res = f3_shared_ram[convert_offset(offset)];#ifdef DUMP fprintf(stderr,"f3_68000_share_r %x(%x)->%x\n",(offset>>1)&0xfff,offset,res);#endif return res;}WRITE_HANDLER( f3_68000_share_wb ) { f3_shared_ram[convert_offset(offset)]=data;#ifdef DUMP fprintf(stderr,"f3_68000_share_w %x,%x\n",(offset>>1)&0xfff,data);#endif}WRITE16_HANDLER(f3_68000_share_ww){ //offset>>=1; offset &= 0xfff; fprintf(stderr,"ww\n"); WriteWord68k(f3_shared_ram+offset,data);#ifdef DUMP fprintf(stderr,"f3_68000_share_w %x,%x\n",offset,data);#endif //fprintf(stderr,"f3_68000_share_w %x,%x\n",offset,data); //exit(1);}void f3_68681_reset(void){ int7_active = 0; timer_mode = 0; if (timer_68681) { //timer_remove(timer_68681); timer_68681=NULL; }}READ_HANDLER( ES5505_data_0_rb ) { int res = ES5505_data_0_r(offset); if (offset & 1) res &= 0xff; else res>>=8; //fprintf(stderr,"ES5505_data_0_r %x -> %x\n",offset,res); return res;}WRITE_HANDLER( ES5505_data_0_wdebug ) { fprintf(stderr,"ES5505_data_0_wdebug\n");}READ16_HANDLER(f3_68681_rdebug){ fprintf(stderr,"f3_68681_rdebug\n"); return 0;}READ_HANDLER(f3_68681_rb){ int ret; offset>>=1; offset &= 0x1f; if (offset==0x5) { ret=imr_status; imr_status=0; // logerror("%06x: 68681 read offset %04x (%04x)\n",cpu_get_pc(),offset,ret); } else if (offset==0xe) ret= 1; /* IRQ ack */ else if (offset==0xf) { //cpu_set_irq_line(1, 6, CLEAR_LINE); //cpu_interrupt(CPU_68K_0,6); ret= 0; } else ret= 0xff;#ifdef DUMP fprintf(stderr,"f3_68681_r %x->%x\n",offset,ret);#endif return ret;}WRITE16_HANDLER(f3_68681_wdebug){ fprintf(stderr,"f3_68681_wdebug\n");}void f3_timer_callback() { //WriteLong(&M68000RAM[0x0060+4*7],vector_reg); //if (ReadLong68k(&M68000RAM[vector_reg]) != ReadLong68k(&M68000RAM[0x60+7*4])){ int vec;#ifdef DUMP fprintf(stderr,"setting int7 at %x ram %x s68000context %x\n",vector_reg,ReadLong68k(&M68000RAM[vector_reg*4]),s68000context.interrupts[7]);#endif vec = ReadLong68k(&M68000RAM[vector_reg*4]); /* Only cause IRQ if the mask is set to allow it */ if (m68681_imr&8) { WriteLong68k(&M68000RAM[0x60+4*6],vec); cpu_interrupt(CPU_68K_0,6); imr_status |= 0x8; if (timer_mode){ timer_mode = 0; int7_active = 0; } }#if 0 else { fprintf(stderr,"vec %x (PC:%x)\n",vec,s68000readPC()); if (!vec) { fprintf(stderr,"cycles %d slices %d cpt %d frames %d int %d\n",f3_cycles_68000,f3_slices,mycpt,nb_frames,nb_int); exit(1); } mycpt=nb_frames=nb_int=0; }#endif }//c109e8: 68681 read offset 001c is end of init sequenceWRITE_HANDLER(f3_68681_wb){ offset>>=1; offset &= 0x1f;#ifdef DUMP fprintf(stderr,"f3_68681_wb %x %x (pc:%x)\n",offset,data,s68000readPC());#endif switch (offset) { case 0x04: /* ACR */ // the ACR has been entierly rewritten by Brian (who ?) switch ((data>>4)&7) {#ifdef RAINE_DEBUG case 0: print_debug("Counter: Unimplemented external IP2\n"); break; case 1: print_debug("Counter: Unimplemented TxCA - 1X clock of channel A\n"); break; case 2: print_debug("Counter: Unimplemented TxCB - 1X clock of channel B\n"); break;#endif case 3: #ifdef RAINE_DEBUG print_debug("Counter: X1/Clk - divided by 16, counter is %04x, so interrupt every %d cycles\n",counter,(M68000_CLOCK/M68681_CLOCK)*counter*16);#endif //if (timer_68681) timer_remove(timer_68681); //timer_mode=TIMER_SINGLESHOT; //timer_68681=timer_set(TIME_IN_CYCLES((M68000_CLOCK/M68681_CLOCK)*counter*16,1), 0, timer_callback); f3_cycles_68000 = (M68000_CLOCK/M68681_CLOCK)*counter*16; f3_slices = 16000000/(60*f3_cycles_68000); timer_mode = 1; // single shot int7_active = 1; f3_timer_callback(); //fprintf(stderr,"cycles %d slices %d counter %d\n",f3_cycles_68000,f3_slices,counter); if (!f3_slices) f3_slices = 2; // 2 is a minimum for games with half slices !!! break;#ifdef RAINE_DEBUG case 4: print_debug("Timer: Unimplemented external IP2\n"); break; case 5: print_debug("Timer: Unimplemented external IP2/16\n"); break;#endif case 6: #ifdef RAINE_DEBUG print_debug("Timer: X1/Clk, counter is %04x, so interrupt every %d cycles\n",counter,(M68000_CLOCK/M68681_CLOCK)*counter);#endif //if (timer_68681) timer_remove(timer_68681); //timer_mode=TIMER_PULSE; //timer_68681=timer_pulse(TIME_IN_CYCLES((M68000_CLOCK/M68681_CLOCK)*counter,1), 0, timer_callback); f3_cycles_68000 = (M68000_CLOCK/M68681_CLOCK)*counter; f3_slices = 16000000/(60*f3_cycles_68000); int7_active = 1; //fprintf(stderr,"cycles %d slices %d counter %d\n",f3_cycles_68000,f3_slices,counter); // wait for the next one... break;#ifdef RAINE_DEBUG case 7: print_debug("Timer: Unimplemented X1/Clk - divided by 16\n"); break;#endif } break; case 0x05: /* IMR */ m68681_imr=data&0xff; break; case 0x06: /* CTUR */ counter=((data&0xff)<<8)|(counter&0xff); break; case 0x07: /* CTLR */ counter=(counter&0xff00)|(data&0xff); break; case 0x08: break; /* MR1B (Mode register B) */ case 0x09: break; /* CSRB (Clock select register B) */ case 0x0a: break; /* CRB (Command register B) */ case 0x0b: break; /* TBB (Transmit buffer B) */ case 0x0c: /* IVR (Interrupt vector) */ vector_reg=data&0xff; break; default: break; }}READ_HANDLER(es5510_dsp_rb){ int res; offset &= 0x1ff;#ifdef DUMP fprintf(stderr,"es5510_dsp_rb %x (%d)\n",offset>>1,es_tmp);#endif if (es_tmp) res = ReadByte(((char*)es5510_dsp_ram)+offset); if (offset==0x24) res= 0; else if (offset==0x2c) res= 0x27; else res= ReadByte(((char*)es5510_dsp_ram)+offset);#ifdef DUMP fprintf(stderr,"-> %x\n",res);#endif return res;}READ16_HANDLER(es5510_dsp_r){ offset>>=1; offset &= 0x1ff; // Normally this code is NEVER called...#ifdef DUMP fprintf(stderr,"es5510_dsp_rb %x (%d)\n",offset,es_tmp);#endif if (es_tmp) return es5510_dsp_ram[offset]; /* switch (offset) { case 0x00: return (es5510_gpr_latch>>16)&0xff; case 0x01: return (es5510_gpr_latch>> 8)&0xff; case 0x02: return (es5510_gpr_latch>> 0)&0xff; case 0x03: return 0; } */ // offset<<=1;//if (offset<7 && es5510_dsp_ram[0]!=0xff) return rand()%0xffff; if (offset==0x12) return 0; // if (offset>4) // fprintf(stderr,"%06x: DSP read offset %04x (data is %04x)\n",cpu_get_pc(CPU_68K_0),offset,es5510_dsp_ram[offset]); if (offset==0x16) return 0x27; return es5510_dsp_ram[offset];}?? 快捷鍵說明
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