#if 0
#define PWR_ON()	{Port1_BackUp &= ~bit0;	P1=Port1_BackUp;  }
#define PWR_OFF()	{Port1_BackUp |=  bit0;	P1=Port1_BackUp;  }
#define PWR_LED_TOGGLE(){Port1_BackUp ^=  bit0;	P1=Port1_BackUp;  }
#define Test_LED()	{Port1_BackUp &= ~bit0;	P1=Port1_BackUp;  }
#define CF_LED_ON()	{ }
#define CF_LED_OFF()	{ }
#define CF_LED_TOGGLE() { }
#define MS_LED_ON()	{ }
#define MS_LED_OFF()	{ }
#define MS_LED_TOGGLE() { }
#define SM_LED_ON()	{ }
#define SM_LED_OFF()	{ }
#define SM_LED_TOGGLE() { }
#define SD_LED_ON()	{ }
#define SD_LED_OFF()	{ }
#define SD_LED_TOGGLE() { }
#define XD_LED_ON()	{ }
#define XD_LED_OFF()	{ }
#define XD_LED_TOGGLE() { }



/*
#define LED_GREEN_ON()	{ if (CHK_DUAL) {Port9_BackUp  &=~0x80;	pdP9 = Port9_BackUp ;} \
			  else P35=0; }
#define LED_GREEN_OFF()	{ if (CHK_DUAL) {Port9_BackUp  |= 0x80;	pdP9 = Port9_BackUp ;} \
			  else P35=1; }
#define LED_RED_OFF()	{ if (CHK_DUAL) P35=1; else P35=0; }
#define LED_RED_TOGGLE() {P35^=1;}
#define SM_CE_ENABLE()	{ PortB_BackUp &= ~0x40;	pdPB = PortB_BackUp ; }
#define SM_CE_DISABLE()	{ PortB_BackUp  |= 0x40;	pdPB = PortB_BackUp ; }
#define XD_CE_ENABLE()	{ Port9_BackUp &= ~0x01; 	pdP9 = Port9_BackUp ; }
#define XD_CE_DISABLE()	{ Port9_BackUp  |= 0x01;	pdP9 = Port9_BackUp ; }
#define SM_XD_CE_DISABLE() {SM_CE_DISABLE();  XD_CE_DISABLE(); }
#define CF_POWER_ON()  	{ Port9_BackUp  &=~0x04;	pdP9 = Port9_BackUp ;}
#define CF_POWER_OFF() 	{ Port9_BackUp  |= 0x04;	pdP9 = Port9_BackUp ;}

*/
#define CHK_CF_CARD_DET		1
#define CHK_MS_CARD_DET		1
#define CHK_SD_CARD_DET 	0

#define CHK_SD_WP_DET		0
#define CHK_SM_CARD_DET		1
#define CHK_SM_WP_DET		1
#define CHK_XD_CARD_DET		1
#define CHK_XD_WP_DET		1


#define DAC_MUTE        	P5_2                /* DAC mute port */
#define DAC_DEEM       	 	P5_3                /* DAC de-emphasis port */
#define DAC_CLK         	P3_4                /* DAC CSEL port */

#endif