+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; keymove:u1|key_out1[0]                  ; 9       ;
; keymove:u1|key_out1[1]                  ; 9       ;
; keymove:u1|key_out1[2]                  ; 9       ;
; keymove:u1|key_out1[3]                  ; 9       ;
; keymove:u1|key_out2[0]                  ; 9       ;
; keymove:u1|key_out2[1]                  ; 9       ;
; keymove:u1|key_out2[2]                  ; 9       ;
; keymove:u1|key_out2[3]                  ; 9       ;
; keymove:u1|key_out3[0]                  ; 9       ;
; keymove:u1|key_out3[1]                  ; 9       ;
; keymove:u1|key_out3[2]                  ; 9       ;
; keymove:u1|key_out3[3]                  ; 9       ;
; keymove:u1|key_out4[0]                  ; 8       ;
; keymove:u1|key_out4[1]                  ; 8       ;
; keymove:u1|key_out4[2]                  ; 8       ;
; keymove:u1|key_out4[3]                  ; 8       ;
; Total number of inverted registers = 16 ;         ;
+-----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed May 20 20:42:19 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lock -c lock
Info: Found 2 design units, including 1 entities, in source file lock.vhd
    Info: Found design unit 1: lock-behav
    Info: Found entity 1: lock
Info: Found 2 design units, including 1 entities, in source file ../keymove/keymove.vhd
    Info: Found design unit 1: keymove-key
    Info: Found entity 1: keymove
Info: Found 2 design units, including 1 entities, in source file ../led7/led7.vhd
    Info: Found design unit 1: led7-behav
    Info: Found entity 1: led7
Info: Elaborating entity "lock" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at lock.vhd(52): signal "move" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(57): signal "enter" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(60): signal "key_out1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(60): signal "key_out2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(60): signal "key_out3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(60): signal "key_out4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(61): signal "enter" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "key_out1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "password1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "key_out2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "password2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "key_out3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "password3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "key_out4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(65): signal "password4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(70): signal "initialization" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(74): signal "add" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lock.vhd(75): signal "add" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at lock.vhd(48): inferring latch(es) for signal or variable "password1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at lock.vhd(48): inferring latch(es) for signal or variable "password2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at lock.vhd(48): inferring latch(es) for signal or variable "password3", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at lock.vhd(48): inferring latch(es) for signal or variable "password4", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at lock.vhd(48): inferring latch(es) for signal or variable "add", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "add[0]" at lock.vhd(48)
Info (10041): Inferred latch for "add[1]" at lock.vhd(48)
Info (10041): Inferred latch for "add[2]" at lock.vhd(48)
Info (10041): Inferred latch for "password4[0]" at lock.vhd(48)
Info (10041): Inferred latch for "password4[1]" at lock.vhd(48)
Info (10041): Inferred latch for "password4[2]" at lock.vhd(48)
Info (10041): Inferred latch for "password4[3]" at lock.vhd(48)
Info (10041): Inferred latch for "password3[0]" at lock.vhd(48)
Info (10041): Inferred latch for "password3[1]" at lock.vhd(48)
Info (10041): Inferred latch for "password3[2]" at lock.vhd(48)
Info (10041): Inferred latch for "password3[3]" at lock.vhd(48)
Info (10041): Inferred latch for "password2[0]" at lock.vhd(48)
Info (10041): Inferred latch for "password2[1]" at lock.vhd(48)
Info (10041): Inferred latch for "password2[2]" at lock.vhd(48)
Info (10041): Inferred latch for "password2[3]" at lock.vhd(48)
Info (10041): Inferred latch for "password1[0]" at lock.vhd(48)
Info (10041): Inferred latch for "password1[1]" at lock.vhd(48)
Info (10041): Inferred latch for "password1[2]" at lock.vhd(48)
Info (10041): Inferred latch for "password1[3]" at lock.vhd(48)
Info: Elaborating entity "keymove" for hierarchy "keymove:u1"
Warning (10492): VHDL Process Statement warning at keymove.vhd(32): signal "keyreset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keymove.vhd(32): signal "clear" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "led7" for hierarchy "keymove:u1|led7:u1"
Info: State machine "|lock|current_state" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|lock|current_state"
Info: Encoding result for state machine "|lock|current_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "current_state.st5"
        Info: Encoded state bit "current_state.st4"
        Info: Encoded state bit "current_state.st3"
        Info: Encoded state bit "current_state.st2"
        Info: Encoded state bit "current_state.st1"
        Info: Encoded state bit "current_state.st0"
    Info: State "|lock|current_state.st0" uses code string "000000"
    Info: State "|lock|current_state.st1" uses code string "000011"
    Info: State "|lock|current_state.st2" uses code string "000101"
    Info: State "|lock|current_state.st3" uses code string "001001"
    Info: State "|lock|current_state.st4" uses code string "010001"
    Info: State "|lock|current_state.st5" uses code string "100001"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 177 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 30 output pins
    Info: Implemented 132 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Wed May 20 20:42:22 2009
    Info: Elapsed time: 00:00:03