?? lock.tan.qmsg
字號:
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 17 " "Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "keymove:u1\|keyout2\[1\] password2\[1\] clk 2.817 ns " "Info: Found hold time violation between source pin or register \"keymove:u1\|keyout2\[1\]\" and destination pin or register \"password2\[1\]\" for clock \"clk\" (Hold time is 2.817 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.797 ns + Largest " "Info: + Largest clock skew is 3.797 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.457 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'clk'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.905 ns) + CELL(0.787 ns) 3.691 ns current_state.st2 2 REG LCFF_X34_Y7_N9 4 " "Info: 2: + IC(1.905 ns) + CELL(0.787 ns) = 3.691 ns; Loc. = LCFF_X34_Y7_N9; Fanout = 4; REG Node = 'current_state.st2'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.692 ns" { clk current_state.st2 } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.130 ns) + CELL(0.000 ns) 4.821 ns current_state.st2~clkctrl 3 COMB CLKCTRL_G15 16 " "Info: 3: + IC(1.130 ns) + CELL(0.000 ns) = 4.821 ns; Loc. = CLKCTRL_G15; Fanout = 16; COMB Node = 'current_state.st2~clkctrl'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { current_state.st2 current_state.st2~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.361 ns) + CELL(0.275 ns) 6.457 ns password2\[1\] 4 REG LCCOMB_X35_Y7_N0 1 " "Info: 4: + IC(1.361 ns) + CELL(0.275 ns) = 6.457 ns; Loc. = LCCOMB_X35_Y7_N0; Fanout = 1; REG Node = 'password2\[1\]'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.636 ns" { current_state.st2~clkctrl password2[1] } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.061 ns ( 31.92 % ) " "Info: Total cell delay = 2.061 ns ( 31.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.396 ns ( 68.08 % ) " "Info: Total interconnect delay = 4.396 ns ( 68.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.457 ns" { clk current_state.st2 current_state.st2~clkctrl password2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.457 ns" { clk {} clk~combout {} current_state.st2 {} current_state.st2~clkctrl {} password2[1] {} } { 0.000ns 0.000ns 1.905ns 1.130ns 1.361ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.275ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.660 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'clk'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.537 ns) 2.660 ns keymove:u1\|keyout2\[1\] 3 REG LCFF_X35_Y7_N31 2 " "Info: 3: + IC(1.006 ns) + CELL(0.537 ns) = 2.660 ns; Loc. = LCFF_X35_Y7_N31; Fanout = 2; REG Node = 'keymove:u1\|keyout2\[1\]'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.543 ns" { clk~clkctrl keymove:u1|keyout2[1] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.74 % ) " "Info: Total cell delay = 1.536 ns ( 57.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.124 ns ( 42.26 % ) " "Info: Total interconnect delay = 1.124 ns ( 42.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { clk clk~clkctrl keymove:u1|keyout2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { clk {} clk~combout {} clk~clkctrl {} keymove:u1|keyout2[1] {} } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.457 ns" { clk current_state.st2 current_state.st2~clkctrl password2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.457 ns" { clk {} clk~combout {} current_state.st2 {} current_state.st2~clkctrl {} password2[1] {} } { 0.000ns 0.000ns 1.905ns 1.130ns 1.361ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.275ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { clk clk~clkctrl keymove:u1|keyout2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { clk {} clk~combout {} clk~clkctrl {} keymove:u1|keyout2[1] {} } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.730 ns - Shortest register register " "Info: - Shortest register to register delay is 0.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keymove:u1\|keyout2\[1\] 1 REG LCFF_X35_Y7_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y7_N31; Fanout = 2; REG Node = 'keymove:u1\|keyout2\[1\]'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keymove:u1|keyout2[1] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.311 ns) + CELL(0.419 ns) 0.730 ns password2\[1\] 2 REG LCCOMB_X35_Y7_N0 1 " "Info: 2: + IC(0.311 ns) + CELL(0.419 ns) = 0.730 ns; Loc. = LCCOMB_X35_Y7_N0; Fanout = 1; REG Node = 'password2\[1\]'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { keymove:u1|keyout2[1] password2[1] } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.419 ns ( 57.40 % ) " "Info: Total cell delay = 0.419 ns ( 57.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.311 ns ( 42.60 % ) " "Info: Total interconnect delay = 0.311 ns ( 42.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { keymove:u1|keyout2[1] password2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "0.730 ns" { keymove:u1|keyout2[1] {} password2[1] {} } { 0.000ns 0.311ns } { 0.000ns 0.419ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.457 ns" { clk current_state.st2 current_state.st2~clkctrl password2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.457 ns" { clk {} clk~combout {} current_state.st2 {} current_state.st2~clkctrl {} password2[1] {} } { 0.000ns 0.000ns 1.905ns 1.130ns 1.361ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.275ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { clk clk~clkctrl keymove:u1|keyout2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { clk {} clk~combout {} clk~clkctrl {} keymove:u1|keyout2[1] {} } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { keymove:u1|keyout2[1] password2[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "0.730 ns" { keymove:u1|keyout2[1] {} password2[1] {} } { 0.000ns 0.311ns } { 0.000ns 0.419ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "keymove:u1\|keyout1\[2\] enter clk 6.857 ns register " "Info: tsu for register \"keymove:u1\|keyout1\[2\]\" (data pin = \"enter\", clock pin = \"clk\") is 6.857 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.543 ns + Longest pin register " "Info: + Longest pin to register delay is 9.543 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns enter 1 PIN PIN_G26 5 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 5; PIN Node = 'enter'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { enter } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.646 ns) + CELL(0.420 ns) 7.928 ns Selector0~8 2 COMB LCCOMB_X35_Y7_N10 32 " "Info: 2: + IC(6.646 ns) + CELL(0.420 ns) = 7.928 ns; Loc. = LCCOMB_X35_Y7_N10; Fanout = 32; COMB Node = 'Selector0~8'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.066 ns" { enter Selector0~8 } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.955 ns) + CELL(0.660 ns) 9.543 ns keymove:u1\|keyout1\[2\] 3 REG LCFF_X33_Y8_N19 2 " "Info: 3: + IC(0.955 ns) + CELL(0.660 ns) = 9.543 ns; Loc. = LCFF_X33_Y8_N19; Fanout = 2; REG Node = 'keymove:u1\|keyout1\[2\]'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.615 ns" { Selector0~8 keymove:u1|keyout1[2] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.942 ns ( 20.35 % ) " "Info: Total cell delay = 1.942 ns ( 20.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.601 ns ( 79.65 % ) " "Info: Total interconnect delay = 7.601 ns ( 79.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "9.543 ns" { enter Selector0~8 keymove:u1|keyout1[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "9.543 ns" { enter {} enter~combout {} Selector0~8 {} keymove:u1|keyout1[2] {} } { 0.000ns 0.000ns 6.646ns 0.955ns } { 0.000ns 0.862ns 0.420ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.650 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'clk'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.537 ns) 2.650 ns keymove:u1\|keyout1\[2\] 3 REG LCFF_X33_Y8_N19 2 " "Info: 3: + IC(0.996 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X33_Y8_N19; Fanout = 2; REG Node = 'keymove:u1\|keyout1\[2\]'" { } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { clk~clkctrl keymove:u1|keyout1[2] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.96 % ) " "Info: Total cell delay = 1.536 ns ( 57.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.114 ns ( 42.04 % ) " "Info: Total interconnect delay = 1.114 ns ( 42.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { clk clk~clkctrl keymove:u1|keyout1[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { clk {} clk~combout {} clk~clkctrl {} keymove:u1|keyout1[2] {} } { 0.000ns 0.000ns 0.118ns 0.996ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "9.543 ns" { enter Selector0~8 keymove:u1|keyout1[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "9.543 ns" { enter {} enter~combout {} Selector0~8 {} keymove:u1|keyout1[2] {} } { 0.000ns 0.000ns 6.646ns 0.955ns } { 0.000ns 0.862ns 0.420ns 0.660ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { clk clk~clkctrl keymove:u1|keyout1[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { clk {} clk~combout {} clk~clkctrl {} keymove:u1|keyout1[2] {} } { 0.000ns 0.000ns 0.118ns 0.996ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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