{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 20 21:16:41 2009 " "Info: Processing started: Wed May 20 21:16:41 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off lock -c lock " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lock -c lock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "D:/study/VHDL/lock_cipher/lock/lock.vwf " "Info: Using vector source file \"D:/study/VHDL/lock_cipher/lock/lock.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out1\[0\] " "Info: Register: \|lock\|keymove:u1\|key_out1\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out1\[1\] " "Info: Register: \|lock\|keymove:u1\|key_out1\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out1\[2\] " "Info: Register: \|lock\|keymove:u1\|key_out1\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out1\[3\] " "Info: Register: \|lock\|keymove:u1\|key_out1\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out2\[0\] " "Info: Register: \|lock\|keymove:u1\|key_out2\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out2\[1\] " "Info: Register: \|lock\|keymove:u1\|key_out2\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out2\[2\] " "Info: Register: \|lock\|keymove:u1\|key_out2\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out2\[3\] " "Info: Register: \|lock\|keymove:u1\|key_out2\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out3\[0\] " "Info: Register: \|lock\|keymove:u1\|key_out3\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out3\[1\] " "Info: Register: \|lock\|keymove:u1\|key_out3\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out3\[2\] " "Info: Register: \|lock\|keymove:u1\|key_out3\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out3\[3\] " "Info: Register: \|lock\|keymove:u1\|key_out3\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out4\[0\] " "Info: Register: \|lock\|keymove:u1\|key_out4\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out4\[1\] " "Info: Register: \|lock\|keymove:u1\|key_out4\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out4\[2\] " "Info: Register: \|lock\|keymove:u1\|key_out4\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|lock\|keymove:u1\|key_out4\[3\] " "Info: Register: \|lock\|keymove:u1\|key_out4\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0 "" 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     16.13 % " "Info: Simulation coverage is      16.13 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "1155 " "Info: Number of transitions in simulation is 1155" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "105 " "Info: Allocated 105 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 20 21:16:42 2009 " "Info: Processing ended: Wed May 20 21:16:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}