library ieee;
use ieee.std_logic_1164.all;
entity keymove is
	port(keyin : in std_logic_vector(9 downto 0);
		keyclk,keymove,OE,keyreset,clear: in std_logic;
		keyout4,keyout3,keyout2,keyout1 : out std_logic_vector(3 downto 0);	
	led_out1,led_out2,led_out3,led_out4 : out std_logic_vector(6 downto 0));
	
end entity keymove;

architecture key of keymove is

  component led7
	port( ledin : in  std_logic_vector(3 downto 0);
		 ledout : out std_logic_vector(6 downto 0);
			clk_led7 : in std_logic);
  end component;

signal key_out4,key_out3,key_out2,key_out1 : std_logic_vector(3 downto 0);
  begin
m:	process(keyclk,keymove,OE)
	begin
--	if OE='1' then
	
--	end if;
	if ((OE='1') and (keymove'event and keymove='1')) then 
			key_out4<=key_out3;key_out3<=key_out2;key_out2<=key_out1;
			end if;
--			end if;
--	if clear = '1' then key_out1<="1111";key_out2<="1111";key_out3<="1111";key_out4<="1111";
--	end if;
	if ((keyreset = '0') or (clear = '1')) then key_out1<="1111";key_out2<="1111";key_out3<="1111";key_out4<="1111";
	elsif ((OE='1') and (keyclk'event and keyclk='1')) then 
		case keyin is
		when "0000000001"=>key_out1<="0000";
		when "0000000010"=>key_out1<="0001";
		when "0000000100"=>key_out1<="0010";
		when "0000001000"=>key_out1<="0011";
		when "0000010000"=>key_out1<="0100";
		when "0000100000"=>key_out1<="0101";
		when "0001000000"=>key_out1<="0110";
		when "0010000000"=>key_out1<="0111";
		when "0100000000"=>key_out1<="1000";
		when "1000000000"=>key_out1<="1001";
		when others =>key_out1<="1111";
		end case ;
--		keyout3<=key_out3;keyout2<=key_out2;keyout1<=key_out1;keyout0<=key_out0;
	end if;
--	keyout3<=key_out3;keyout2<=key_out2;keyout1<=key_out1;keyout0<=key_out0;
	end process m;
	
k:process(keyclk,OE)
  begin
	if ((OE='1') and (keyclk'event and keyclk='1'))then keyout4<=key_out4;keyout3<=key_out3;keyout2<=key_out2;keyout1<=key_out1;
	end if;
	end process k;
	
  u1 : led7 port map (ledin=>key_out1,ledout=>led_out1,clk_led7=>keyclk);
  u2 : led7 port map (ledin=>key_out2,ledout=>led_out2,clk_led7=>keyclk);
  u3 : led7 port map (ledin=>key_out3,ledout=>led_out3,clk_led7=>keyclk);
  u4 : led7 port map (ledin=>key_out4,ledout=>led_out4,clk_led7=>keyclk);
	
  end architecture key;