Classic Timing Analyzer report for led7
Fri May 15 19:17:34 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tsu
  6. tco
  7. th
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                     ;
+------------------------------+-------+---------------+-------------+----------------+----------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From           ; To             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------------+----------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 1.048 ns    ; ledin[2]       ; ledout[6]~reg0 ; --         ; clk_led7 ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 6.686 ns    ; ledout[0]~reg0 ; ledout[0]      ; clk_led7   ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.440 ns    ; ledin[3]       ; ledout[4]~reg0 ; --         ; clk_led7 ; 0            ;
; Total number of failed paths ;       ;               ;             ;                ;                ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------------+----------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_led7        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------+
; tsu                                                                      ;
+-------+--------------+------------+----------+----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From     ; To             ; To Clock ;
+-------+--------------+------------+----------+----------------+----------+
; N/A   ; None         ; 1.048 ns   ; ledin[2] ; ledout[6]~reg0 ; clk_led7 ;
; N/A   ; None         ; 1.047 ns   ; ledin[2] ; ledout[3]~reg0 ; clk_led7 ;
; N/A   ; None         ; 1.046 ns   ; ledin[2] ; ledout[0]~reg0 ; clk_led7 ;
; N/A   ; None         ; 1.045 ns   ; ledin[2] ; ledout[1]~reg0 ; clk_led7 ;
; N/A   ; None         ; 1.043 ns   ; ledin[2] ; ledout[2]~reg0 ; clk_led7 ;
; N/A   ; None         ; 1.042 ns   ; ledin[2] ; ledout[4]~reg0 ; clk_led7 ;
; N/A   ; None         ; 1.042 ns   ; ledin[2] ; ledout[5]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.860 ns   ; ledin[1] ; ledout[6]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.859 ns   ; ledin[1] ; ledout[3]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.857 ns   ; ledin[1] ; ledout[1]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.856 ns   ; ledin[1] ; ledout[0]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.854 ns   ; ledin[1] ; ledout[2]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.854 ns   ; ledin[1] ; ledout[4]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.853 ns   ; ledin[1] ; ledout[5]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.543 ns   ; ledin[0] ; ledout[6]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.542 ns   ; ledin[0] ; ledout[0]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.542 ns   ; ledin[0] ; ledout[2]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.542 ns   ; ledin[0] ; ledout[3]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.541 ns   ; ledin[0] ; ledout[1]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.541 ns   ; ledin[0] ; ledout[5]~reg0 ; clk_led7 ;
; N/A   ; None         ; 0.539 ns   ; ledin[0] ; ledout[4]~reg0 ; clk_led7 ;
; N/A   ; None         ; -0.200 ns  ; ledin[3] ; ledout[6]~reg0 ; clk_led7 ;
; N/A   ; None         ; -0.201 ns  ; ledin[3] ; ledout[3]~reg0 ; clk_led7 ;
; N/A   ; None         ; -0.202 ns  ; ledin[3] ; ledout[0]~reg0 ; clk_led7 ;
; N/A   ; None         ; -0.203 ns  ; ledin[3] ; ledout[1]~reg0 ; clk_led7 ;