The 2 important dipswitches are configured as shown below:SW1 (for 33MHz SysClk)----------------------S1   S2   S3   S4   S5   S6   S7   S8OFF  OFF  OFF  OFF  OFF  OFF  OFF  ONSW7 (for Op-Code Flash and Boot Option H)-----------------------------------------S1   S2   S3   S4   S5   S6   S7   S8OFF  OFF  OFF  ON   OFF  OFF  OFF  OFFThe EEPROM at location 0x52 is loaded with these 16 bytes:C47042A6 05D7A190 40082350 0d050000SDR0_SDSTP0[ENG]:	1		: PLL's VCO is the source for PLL forward divisorsSDR0_SDSTP0[SRC]:	1		: Feedback originates from PLLOUTBSDR0_SDSTP0[SEL]:	0		: Feedback selection is PLL outputSDR0_SDSTP0[TUNE]:	1000111000	: 10 <= M <= 22, 600MHz < VCO <= 900MHzSDR0_SDSTP0[FBDV]:	4		: PLL feedback divisorSDR0_SDSTP0[FBDVA]:	2		: PLL forward divisor ASDR0_SDSTP0[FBDVB]:	5		: PLL forward divisor BSDR0_SDSTP0[PRBDV0]:	1		: PLL primary divisor BSDR0_SDSTP0[OPBDV0]:	2		: OPB clock divisorSDR0_SDSTP0[LFBDV]:	1		: PLL local feedback divisorSDR0_SDSTP0[PERDV0]:	3		: Peripheral clock divisor 0SDR0_SDSTP0[MALDV0]:	2		: MAL clock divisor 0SDR0_SDSTP0[PCIDV0]:	2		: Sync PCI clock divisor 0SDR0_SDSTP0[PLLTIMER]:	7		: PLL locking timerSDR0_SDSTP0[RW]:	1		: EBC ROM width: 16-bitSDR0_SDSTP0[RL]:	0		: EBC ROM location: EBCSDR0_SDSTP0[PAE]:	0		: PCI internal arbiter: disabledSDR0_SDSTP0[PHCE]:	0		: PCI host configuration: disabledSDR0_SDSTP0[ZM]:	3		: ZMII mode: RMII mode 100SDR0_SDSTP0[CTE]:	0		: CPU trace: disabledSDR0_SDSTP0[Nto1]:	0		: CPU/PLB ratio N/P: not N to 1SDR0_SDSTP0[PAME]:	1		: PCI asynchronous mode: enabledSDR0_SDSTP0[MEM]:	1		: Multiplex: EMACSDR0_SDSTP0[NE]:	0		: NDFC: disabledSDR0_SDSTP0[NBW]:	0		: NDFC boot width: 8-bitSDR0_SDSTP0[NBW]:	0		: NDFC boot page selectionSDR0_SDSTP0[NBAC]:	0		: NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)SDR0_SDSTP0[NARE]:	0		: NDFC auto read : disabledSDR0_SDSTP0[NRB]:	0		: NDFC Ready/Busy : ReadySDR0_SDSTP0[NDRSC]:	33333		: NDFC device reset counterSDR0_SDSTP0[NCG0]:	0		: NDFC/EBC chip select gating CS0 : EBCSDR0_SDSTP0[NCG1]:	0		: NDFC/EBC chip select gating CS1 : EBCSDR0_SDSTP0[NCG2]:	0		: NDFC/EBC chip select gating CS2 : EBCSDR0_SDSTP0[NCG3]:	0		: NDFC/EBC chip select gating CS3 : EBCSDR0_SDSTP0[NCRDC]:	3333		: NDFC device read countPPC440EP Clocking ConfigurationSysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHzOPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHzThe above information is reported by Eugene O'Brien<Eugene.O'Brien@advantechamt.com>. Thanks a lot.2007-08-06, Stefan Roese <sr@denx.de>---------------------------------------------------------------------The configuration for the AMCC 440EP eval board "Bamboo" was changedto only use 384 kbytes of FLASH for the U-Boot image. This way theredundant environment can be saved in the remaining 2 sectors of thesame flash chip.Caution: With an upgrade from an earlier U-Boot version the currentenvironment will be erased since the environment is now saved indifferent sectors. By using the following command the environment canbe saved after upgrading the U-Boot image and *before* resetting theboard:setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \	'cp.b FFF60000 FFF80000 20000'2006-07-27, Stefan Roese <sr@denx.de>