/* * Copyright 2007 Wind River Systems <www.windriver.com> * Copyright 2007 Embedded Specialties, Inc. * Joe Hamman <joe.hamman@embeddedspecialties.com> * * Copyright 2006 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * SBC8641D board configuration file * * Make sure you change the MAC address and other network params first, * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. */#ifndef __CONFIG_H#define __CONFIG_H/* High Level Configuration Options */#define CONFIG_MPC86xx		1	/* MPC86xx */#define CONFIG_MPC8641		1	/* MPC8641 specific */#define CONFIG_SBC8641D		1	/* SBC8641D board specific */#define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */#ifdef RUN_DIAG#define CFG_DIAG_ADDR        0xff800000#endif#define CFG_RESET_ADDRESS    0xfff00100#define CONFIG_PCI		1	/* Enable PCIE */#define CONFIG_PCI1		1	/* PCIE controler 1 (slot 1) */#define CONFIG_PCI2		1	/* PCIE controler 2 (slot 2) */#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */#define CONFIG_TSEC_ENET 		/* tsec ethernet support */#define CONFIG_ENV_OVERWRITE#undef CONFIG_SPD_EEPROM		/* Do not use SPD EEPROM for DDR setup*/#undef CONFIG_DDR_DLL			/* possible DLL fix needed */#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */#undef CONFIG_DDR_ECC  			/* only for ECC DDR module */#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */#define CONFIG_MEM_INIT_VALUE		0xDeadBeef#define CONFIG_NUM_DDR_CONTROLLERS     2#define CACHE_LINE_INTERLEAVING		0x20000000#define PAGE_INTERLEAVING		0x21000000#define BANK_INTERLEAVING		0x22000000#define SUPER_BANK_INTERLEAVING		0x23000000#define CONFIG_ALTIVEC          1/* * L2CR setup -- make sure this is right for your board! */#define CFG_L2#define L2_INIT		0#define L2_ENABLE	(L2CR_L2E)#ifndef CONFIG_SYS_CLK_FREQ#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)#endif#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */#undef	CFG_DRAM_TEST				/* memory test, takes time */#define CFG_MEMTEST_START	0x00200000	/* memtest region */#define CFG_MEMTEST_END		0x00400000/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */#define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)#define CFG_PCI2_ADDR		(CFG_CCSRBAR+0x9000)/* * DDR Setup */#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory */#define CFG_DDR_SDRAM_BASE2	0x10000000	/* DDR bank 2 */#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE#define CFG_SDRAM_BASE2		CFG_DDR_SDRAM_BASE2#define CONFIG_VERY_BIG_RAM#define MPC86xx_DDR_SDRAM_CLK_CNTL#if defined(CONFIG_SPD_EEPROM)    /*     * Determine DDR configuration from I2C interface.     */    #define SPD_EEPROM_ADDRESS1		0x51		/* DDR DIMM */    #define SPD_EEPROM_ADDRESS2		0x52		/* DDR DIMM */    #define SPD_EEPROM_ADDRESS3		0x53		/* DDR DIMM */    #define SPD_EEPROM_ADDRESS4		0x54		/* DDR DIMM */#else    /*     * Manually set up DDR1 & DDR2 parameters     */    #define CFG_SDRAM_SIZE	512		/* DDR is 512MB */    #define CFG_DDR_CS0_BNDS	0x0000000F    #define CFG_DDR_CS1_BNDS	0x00000000    #define CFG_DDR_CS2_BNDS	0x00000000    #define CFG_DDR_CS3_BNDS	0x00000000    #define CFG_DDR_CS0_CONFIG	0x80010102    #define CFG_DDR_CS1_CONFIG	0x00000000    #define CFG_DDR_CS2_CONFIG	0x00000000    #define CFG_DDR_CS3_CONFIG	0x00000000    #define CFG_DDR_EXT_REFRESH 0x00000000    #define CFG_DDR_TIMING_0	0x00220802    #define CFG_DDR_TIMING_1	0x38377322    #define CFG_DDR_TIMING_2	0x002040c7    #define CFG_DDR_CFG_1A	0x43008008    #define CFG_DDR_CFG_2	0x24401000    #define CFG_DDR_MODE_1	0x23c00542    #define CFG_DDR_MODE_2	0x00000000    #define CFG_DDR_MODE_CTL	0x00000000    #define CFG_DDR_INTERVAL	0x05080100    #define CFG_DDR_DATA_INIT	0x00000000    #define CFG_DDR_CLK_CTRL	0x03800000    #define CFG_DDR_CFG_1B	0xC3008008    #define CFG_DDR2_CS0_BNDS	0x0010001F    #define CFG_DDR2_CS1_BNDS	0x00000000    #define CFG_DDR2_CS2_BNDS	0x00000000    #define CFG_DDR2_CS3_BNDS	0x00000000    #define CFG_DDR2_CS0_CONFIG	0x80010102    #define CFG_DDR2_CS1_CONFIG	0x00000000    #define CFG_DDR2_CS2_CONFIG	0x00000000    #define CFG_DDR2_CS3_CONFIG	0x00000000    #define CFG_DDR2_EXT_REFRESH 0x00000000    #define CFG_DDR2_TIMING_0	0x00220802    #define CFG_DDR2_TIMING_1	0x38377322    #define CFG_DDR2_TIMING_2	0x002040c7    #define CFG_DDR2_CFG_1A	0x43008008    #define CFG_DDR2_CFG_2	0x24401000    #define CFG_DDR2_MODE_1	0x23c00542    #define CFG_DDR2_MODE_2	0x00000000    #define CFG_DDR2_MODE_CTL	0x00000000    #define CFG_DDR2_INTERVAL	0x05080100    #define CFG_DDR2_DATA_INIT	0x00000000    #define CFG_DDR2_CLK_CTRL	0x03800000    #define CFG_DDR2_CFG_1B	0xC3008008#endif/* #define CFG_ID_EEPROM	1#define ID_EEPROM_ADDR 0x57 *//* * The SBC8641D contains 16MB flash space at ff000000. */#define CFG_FLASH_BASE      0xff000000  /* start of FLASH 16M *//* Flash */#define CFG_BR0_PRELIM		0xff001001	/* port size 16bit */#define CFG_OR0_PRELIM		0xff006e65	/* 16MB Boot Flash area *//* 64KB EEPROM */#define CFG_BR1_PRELIM		0xf0000801	/* port size 16bit */#define CFG_OR1_PRELIM		0xffff6e65	/* 64K EEPROM area *//* EPLD - User switches, board id, LEDs */#define CFG_BR2_PRELIM		0xf1000801	/* port size 16bit */#define CFG_OR2_PRELIM		0xfff06e65	/* EPLD (switches, board ID, LEDs) area *//* Local bus SDRAM 128MB */#define CFG_BR3_PRELIM		0xe0001861	/* port size ?bit */#define CFG_OR3_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (1st half) */#define CFG_BR4_PRELIM		0xe4001861	/* port size ?bit */#define CFG_OR4_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (2nd half) *//* Disk on Chip (DOC) 128MB */#define CFG_BR5_PRELIM		0xe8001001	/* port size ?bit */#define CFG_OR5_PRELIM		0xf8006e65	/* 128MB local bus SDRAM area (2nd half) *//* LCD */#define CFG_BR6_PRELIM		0xf4000801	/* port size ?bit */#define CFG_OR6_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) *//* Control logic & misc peripherals */#define CFG_BR7_PRELIM		0xf2000801	/* port size ?bit */#define CFG_OR7_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */#define CFG_MAX_FLASH_BANKS	1		/* number of banks */#define CFG_MAX_FLASH_SECT	131		/* sectors per device */#undef	CFG_FLASH_CHECKSUM#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */#define CFG_FLASH_CFI_DRIVER#define CFG_FLASH_CFI#define CFG_WRITE_SWAPPED_DATA#define CFG_FLASH_EMPTY_INFO#define CFG_FLASH_PROTECTION#undef CONFIG_CLOCKS_IN_MHZ#define CONFIG_L1_INIT_RAM#define CFG_INIT_RAM_LOCK	1#ifndef CFG_INIT_RAM_LOCK#define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */#else#define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */#endif#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc *//* Serial Port */#define CONFIG_CONS_INDEX     1#undef	CONFIG_SERIAL_SOFTWARE_FIFO#define CFG_NS16550#define CFG_NS16550_SERIAL#define CFG_NS16550_REG_SIZE    1#define CFG_NS16550_CLK		get_bus_freq(0)#define CFG_BAUDRATE_TABLE  \	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)/* Use the HUSH parser */#define CFG_HUSH_PARSER#ifdef  CFG_HUSH_PARSER#define CFG_PROMPT_HUSH_PS2 "> "#endif/* * Pass open firmware flat tree to kernel */#define CONFIG_OF_FLAT_TREE	1#define CONFIG_OF_BOARD_SETUP	1#define OF_CPU		"PowerPC,8641@0"#define OF_SOC		"soc@f8000000"#define OF_TBCLK	(bd->bi_busfreq / 4)#define OF_STDOUT_PATH	"/soc@f8000000/serial@4500"#define CFG_64BIT_VSPRINTF	1#define CFG_64BIT_STRTOUL	1/* * I2C */#define	CONFIG_FSL_I2C		/* Use FSL common I2C driver */#define	CONFIG_HARD_I2C		/* I2C with hardware support*/#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */#define CFG_I2C_SLAVE		0x7F#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */#define CFG_I2C_OFFSET		0x3100/* * RapidIO MMU */#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M *//* * General PCI * Addresses are mapped 1-1. */#define CFG_PCI1_MEM_BASE	0x80000000#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE