/* * mcf5329.h -- Definitions for Freescale Coldfire 5329 * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef mcf5329_h#define mcf5329_h/****************************************************************************//********************************************************************** System Control Module (SCM)*********************************************************************//* Bit definitions and macros for SCM_MPR */#define SCM_MPR_MPROT0(x)		(((x)&0x0F)<<28)#define SCM_MPR_MPROT1(x)		(((x)&0x0F)<<24)#define SCM_MPR_MPROT2(x)		(((x)&0x0F)<<20)#define SCM_MPR_MPROT4(x)		(((x)&0x0F)<<12)#define SCM_MPR_MPROT5(x)		(((x)&0x0F)<<8)#define SCM_MPR_MPROT6(x)		(((x)&0x0F)<<4)#define MPROT_MTR			4#define MPROT_MTW			2#define MPROT_MPL			1/* Bit definitions and macros for SCM_BMT */#define BMT_BME				(0x08)#define BMT_8				(0x07)#define BMT_16				(0x06)#define BMT_32				(0x05)#define BMT_64				(0x04)#define BMT_128				(0x03)#define BMT_256				(0x02)#define BMT_512				(0x01)#define BMT_1024			(0x00)/* Bit definitions and macros for SCM_PACRA */#define SCM_PACRA_PACR0(x)		(((x)&0x0F)<<28)#define SCM_PACRA_PACR1(x)		(((x)&0x0F)<<24)#define SCM_PACRA_PACR2(x)		(((x)&0x0F)<<20)#define PACR_SP	4#define PACR_WP	2#define PACR_TP	1/* Bit definitions and macros for SCM_PACRB */#define SCM_PACRB_PACR8(x)		(((x)&0x0F)<<28)#define SCM_PACRB_PACR12(x)		(((x)&0x0F)<<12)/* Bit definitions and macros for SCM_PACRC */#define SCM_PACRC_PACR16(x)		(((x)&0x0F)<<28)#define SCM_PACRC_PACR17(x)		(((x)&0x0F)<<24)#define SCM_PACRC_PACR18(x)		(((x)&0x0F)<<20)#define SCM_PACRC_PACR19(x)		(((x)&0x0F)<<16)#define SCM_PACRC_PACR21(x)		(((x)&0x0F)<<8)#define SCM_PACRC_PACR22(x)		(((x)&0x0F)<<4)#define SCM_PACRC_PACR23(x)		(((x)&0x0F)<<0)/* Bit definitions and macros for SCM_PACRD */#define SCM_PACRD_PACR24(x)		(((x)&0x0F)<<28)#define SCM_PACRD_PACR25(x)		(((x)&0x0F)<<24)#define SCM_PACRD_PACR26(x)		(((x)&0x0F)<<20)#define SCM_PACRD_PACR28(x)		(((x)&0x0F)<<12)#define SCM_PACRD_PACR29(x)		(((x)&0x0F)<<8)#define SCM_PACRD_PACR30(x)		(((x)&0x0F)<<4)#define SCM_PACRD_PACR31(x)		(((x)&0x0F)<<0)/* Bit definitions and macros for SCM_PACRE */#define SCM_PACRE_PACR32(x)		(((x)&0x0F)<<28)#define SCM_PACRE_PACR33(x)		(((x)&0x0F)<<24)#define SCM_PACRE_PACR34(x)		(((x)&0x0F)<<20)#define SCM_PACRE_PACR35(x)		(((x)&0x0F)<<16)#define SCM_PACRE_PACR36(x)		(((x)&0x0F)<<12)#define SCM_PACRE_PACR37(x)		(((x)&0x0F)<<8)#define SCM_PACRE_PACR38(x)		(((x)&0x0F)<<4)/* Bit definitions and macros for SCM_PACRF */#define SCM_PACRF_PACR40(x)		(((x)&0x0F)<<28)#define SCM_PACRF_PACR41(x)		(((x)&0x0F)<<24)#define SCM_PACRF_PACR42(x)		(((x)&0x0F)<<20)#define SCM_PACRF_PACR43(x)		(((x)&0x0F)<<16)#define SCM_PACRF_PACR44(x)		(((x)&0x0F)<<12)#define SCM_PACRF_PACR45(x)		(((x)&0x0F)<<8)#define SCM_PACRF_PACR46(x)		(((x)&0x0F)<<4)#define SCM_PACRF_PACR47(x)		(((x)&0x0F)<<0)/* Bit definitions and macros for SCM_PACRG */#define SCM_PACRG_PACR48(x)		(((x)&0x0F)<<28)/* Bit definitions and macros for SCM_PACRH */#define SCM_PACRH_PACR56(x)		(((x)&0x0F)<<28)#define SCM_PACRH_PACR57(x)		(((x)&0x0F)<<24)#define SCM_PACRH_PACR58(x)		(((x)&0x0F)<<20)/* PACRn Assignments */#define PACR0(x)			SCM_PACRA_PACR0(x)#define PACR1(x)			SCM_PACRA_PACR1(x)#define PACR2(x)			SCM_PACRA_PACR2(x)#define PACR8(x)			SCM_PACRB_PACR8(x)#define PACR12(x)			SCM_PACRB_PACR12(x)#define PACR16(x)			SCM_PACRC_PACR16(x)#define PACR17(x)			SCM_PACRC_PACR17(x)#define PACR18(x)			SCM_PACRC_PACR18(x)#define PACR19(x)			SCM_PACRC_PACR19(x)#define PACR21(x)			SCM_PACRC_PACR21(x)#define PACR22(x)			SCM_PACRC_PACR22(x)#define PACR23(x)			SCM_PACRC_PACR23(x)#define PACR24(x)			SCM_PACRD_PACR24(x)#define PACR25(x)			SCM_PACRD_PACR25(x)#define PACR26(x)			SCM_PACRD_PACR26(x)#define PACR28(x)			SCM_PACRD_PACR28(x)#define PACR29(x)			SCM_PACRD_PACR29(x)#define PACR30(x)			SCM_PACRD_PACR30(x)#define PACR31(x)			SCM_PACRD_PACR31(x)#define PACR32(x)			SCM_PACRE_PACR32(x)#define PACR33(x)			SCM_PACRE_PACR33(x)#define PACR34(x)			SCM_PACRE_PACR34(x)#define PACR35(x)			SCM_PACRE_PACR35(x)#define PACR36(x)			SCM_PACRE_PACR36(x)#define PACR37(x)			SCM_PACRE_PACR37(x)#define PACR38(x)			SCM_PACRE_PACR38(x)#define PACR40(x)			SCM_PACRF_PACR40(x)#define PACR41(x)			SCM_PACRF_PACR41(x)#define PACR42(x)			SCM_PACRF_PACR42(x)#define PACR43(x)			SCM_PACRF_PACR43(x)#define PACR44(x)			SCM_PACRF_PACR44(x)#define PACR45(x)			SCM_PACRF_PACR45(x)#define PACR46(x)			SCM_PACRF_PACR46(x)#define PACR47(x)			SCM_PACRF_PACR47(x)#define PACR48(x)			SCM_PACRG_PACR48(x)#define PACR56(x)			SCM_PACRH_PACR56(x)#define PACR57(x)			SCM_PACRH_PACR57(x)#define PACR58(x)			SCM_PACRH_PACR58(x)/* Bit definitions and macros for SCM_CWCR */#define CWCR_RO				(0x8000)#define CWCR_CWR_WH			(0x0100)#define CWCR_CWE			(0x0080)#define CWRI_WINDOW			(0x0060)#define CWRI_RESET			(0x0040)#define CWRI_INT_RESET			(0x0020)#define CWRI_INT			(0x0000)#define CWCR_CWT(x)			(((x)&0x001F))/* Bit definitions and macros for SCM_ISR */#define SCMISR_CFEI			(0x02)#define SCMISR_CWIC			(0x01)/* Bit definitions and macros for SCM_BCR */#define BCR_GBR				(0x00000200)#define BCR_GBW				(0x00000100)#define BCR_S7				(0x00000080)#define BCR_S6				(0x00000040)#define BCR_S4				(0x00000010)#define BCR_S1				(0x00000002)/* Bit definitions and macros for SCM_CFIER */#define CFIER_ECFEI			(0x01)/* Bit definitions and macros for SCM_CFLOC */#define CFLOC_LOC			(0x80)/* Bit definitions and macros for SCM_CFATR */#define CFATR_WRITE			(0x80)#define CFATR_SZ32			(0x20)#define CFATR_SZ16			(0x10)#define CFATR_SZ08			(0x00)#define CFATR_CACHE			(0x08)#define CFATR_MODE			(0x02)#define CFATR_TYPE			(0x01)/********************************************************************** FlexBus Chip Selects (FBCS)*********************************************************************//* Bit definitions and macros for FBCS_CSAR */#define CSAR_BA(x)			(((x)&0xFFFF)<<16)/* Bit definitions and macros for FBCS_CSMR */#define CSMR_BAM(x)			(((x)&0xFFFF)<<16)#define CSMR_BAM_4G			(0xFFFF0000)#define CSMR_BAM_2G			(0x7FFF0000)#define CSMR_BAM_1G			(0x3FFF0000)#define CSMR_BAM_1024M			(0x3FFF0000)#define CSMR_BAM_512M			(0x1FFF0000)#define CSMR_BAM_256M			(0x0FFF0000)#define CSMR_BAM_128M			(0x07FF0000)#define CSMR_BAM_64M			(0x03FF0000)#define CSMR_BAM_32M			(0x01FF0000)#define CSMR_BAM_16M			(0x00FF0000)#define CSMR_BAM_8M			(0x007F0000)#define CSMR_BAM_4M			(0x003F0000)#define CSMR_BAM_2M			(0x001F0000)#define CSMR_BAM_1M			(0x000F0000)#define CSMR_BAM_1024K			(0x000F0000)#define CSMR_BAM_512K			(0x00070000)#define CSMR_BAM_256K			(0x00030000)#define CSMR_BAM_128K			(0x00010000)#define CSMR_BAM_64K			(0x00000000)#define CSMR_WP				(0x00000100)#define CSMR_V				(0x00000001)/* Bit definitions and macros for FBCS_CSCR */#define CSCR_SWS(x)			(((x)&0x3F)<<26)#define CSCR_ASET(x)			(((x)&0x03)<<20)#define CSCR_SWSEN			(0x00800000)#define CSCR_ASET_4CLK			(0x00300000)#define CSCR_ASET_3CLK			(0x00200000)#define CSCR_ASET_2CLK			(0x00100000)#define CSCR_ASET_1CLK			(0x00000000)#define CSCR_RDAH(x)			(((x)&0x03)<<18)#define CSCR_RDAH_4CYC			(0x000C0000)#define CSCR_RDAH_3CYC			(0x00080000)#define CSCR_RDAH_2CYC			(0x00040000)#define CSCR_RDAH_1CYC			(0x00000000)#define CSCR_WRAH(x)			(((x)&0x03)<<16)#define CSCR_WDAH_4CYC			(0x00003000)#define CSCR_WDAH_3CYC			(0x00002000)#define CSCR_WDAH_2CYC			(0x00001000)#define CSCR_WDAH_1CYC			(0x00000000)#define CSCR_WS(x)			(((x)&0x3F)<<10)#define CSCR_SBM			(0x00000200)#define CSCR_AA				(0x00000100)#define CSCR_PS_MASK			(0x000000C0)#define CSCR_PS_32			(0x00000000)#define CSCR_PS_16			(0x00000080)#define CSCR_PS_8			(0x00000040)#define CSCR_BEM			(0x00000020)#define CSCR_BSTR			(0x00000010)#define CSCR_BSTW			(0x00000008)/********************************************************************** Reset Controller Module (RCM)*********************************************************************//* Bit definitions and macros for RCR */#define RCM_RCR_FRCRSTOUT		(0x40)#define RCM_RCR_SOFTRST			(0x80)/* Bit definitions and macros for RSR */#define RCM_RSR_LOL			(0x01)#define RCM_RSR_WDR_CORE		(0x02)#define RCM_RSR_EXT			(0x04)#define RCM_RSR_POR			(0x08)#define RCM_RSR_SOFT			(0x20)/********************************************************************** FlexCAN Module (CAN)*********************************************************************//* Bit definitions and macros for CAN_CANMCR */#define CANMCR_MDIS			(0x80000000)#define CANMCR_FRZ			(0x40000000)#define CANMCR_HALT			(0x10000000)#define CANMCR_NORDY			(0x08000000)#define CANMCR_SOFTRST			(0x02000000)#define CANMCR_FRZACK			(0x01000000)#define CANMCR_SUPV			(0x00800000)#define CANMCR_LPMACK			(0x00100000)#define CANMCR_MAXMB(x)			(((x)&0x0F))/* Bit definitions and macros for CAN_CANCTRL */#define CANCTRL_PRESDIV(x)		(((x)&0xFF)<<24)#define CANCTRL_RJW(x)			(((x)&0x03)<<22)#define CANCTRL_PSEG1(x)		(((x)&0x07)<<19)#define CANCTRL_PSEG2(x)		(((x)&0x07)<<16)#define CANCTRL_BOFFMSK			(0x00008000)#define CANCTRL_ERRMSK			(0x00004000)#define CANCTRL_CLKSRC			(0x00002000)#define CANCTRL_LPB			(0x00001000)#define CANCTRL_SMP			(0x00000080)#define CANCTRL_BOFFREC			(0x00000040)#define CANCTRL_TSYNC			(0x00000020)#define CANCTRL_LBUF			(0x00000010)#define CANCTRL_LOM			(0x00000008)#define CANCTRL_PROPSEG(x)		(((x)&0x07))/* Bit definitions and macros for CAN_TIMER */#define TIMER_TIMER(x)			((x)&0xFFFF)/* Bit definitions and macros for CAN_RXGMASK */#define RXGMASK_MI(x)			((x)&0x1FFFFFFF)/* Bit definitions and macros for CAN_ERRCNT */#define ERRCNT_TXECTR(x)		(((x)&0xFF))#define ERRCNT_RXECTR(x)		(((x)&0xFF)<<8)/* Bit definitions and macros for CAN_ERRSTAT */#define ERRSTAT_BITERR1			(0x00008000)#define ERRSTAT_BITERR0			(0x00004000)#define ERRSTAT_ACKERR			(0x00002000)#define ERRSTAT_CRCERR			(0x00001000)#define ERRSTAT_FRMERR			(0x00000800)#define ERRSTAT_STFERR			(0x00000400)#define ERRSTAT_TXWRN			(0x00000200)#define ERRSTAT_RXWRN			(0x00000100)#define ERRSTAT_IDLE			(0x00000080)#define ERRSTAT_TXRX			(0x00000040)#define ERRSTAT_FLT_BUSOFF		(0x00000020)#define ERRSTAT_FLT_PASSIVE		(0x00000010)#define ERRSTAT_FLT_ACTIVE		(0x00000000)#define ERRSTAT_BOFFINT			(0x00000004)#define ERRSTAT_ERRINT			(0x00000002)#define ERRSTAT_WAKINT			(0x00000001)/* Bit definitions and macros for CAN_IMASK */#define IMASK_BUF15M			(0x00008000)#define IMASK_BUF14M			(0x00004000)#define IMASK_BUF13M			(0x00002000)#define IMASK_BUF12M			(0x00001000)#define IMASK_BUF11M			(0x00000800)#define IMASK_BUF10M			(0x00000400)#define IMASK_BUF9M			(0x00000200)#define IMASK_BUF8M			(0x00000100)#define IMASK_BUF7M			(0x00000080)#define IMASK_BUF6M			(0x00000040)#define IMASK_BUF5M			(0x00000020)#define IMASK_BUF4M			(0x00000010)#define IMASK_BUF3M			(0x00000008)#define IMASK_BUF2M			(0x00000004)#define IMASK_BUF1M			(0x00000002)#define IMASK_BUF0M			(0x00000001)/* Bit definitions and macros for CAN_IFLAG */#define IFLAG_BUF15I			(0x00008000)#define IFLAG_BUF14I			(0x00004000)#define IFLAG_BUF13I			(0x00002000)#define IFLAG_BUF12I			(0x00001000)#define IFLAG_BUF11I			(0x00000800)#define IFLAG_BUF10I			(0x00000400)#define IFLAG_BUF9I			(0x00000200)#define IFLAG_BUF8I			(0x00000100)#define IFLAG_BUF7I			(0x00000080)#define IFLAG_BUF6I			(0x00000040)#define IFLAG_BUF5I			(0x00000020)#define IFLAG_BUF4I			(0x00000010)#define IFLAG_BUF3I			(0x00000008)#define IFLAG_BUF2I			(0x00000004)#define IFLAG_BUF1I			(0x00000002)#define IFLAG_BUF0I			(0x00000001)/********************************************************************** Interrupt Controller (INTC)*********************************************************************/#define INTC0_EPORT			INTC_IPRL_INT1#define INT0_LO_RSVD0			(0)#define INT0_LO_EPORT1			(1)#define INT0_LO_EPORT2			(2)#define INT0_LO_EPORT3			(3)#define INT0_LO_EPORT4			(4)#define INT0_LO_EPORT5			(5)#define INT0_LO_EPORT6			(6)#define INT0_LO_EPORT7			(7)#define INT0_LO_EDMA_00			(8)#define INT0_LO_EDMA_01			(9)#define INT0_LO_EDMA_02			(10)#define INT0_LO_EDMA_03			(11)#define INT0_LO_EDMA_04			(12)#define INT0_LO_EDMA_05			(13)#define INT0_LO_EDMA_06			(14)#define INT0_LO_EDMA_07			(15)#define INT0_LO_EDMA_08			(16)#define INT0_LO_EDMA_09			(17)#define INT0_LO_EDMA_10			(18)#define INT0_LO_EDMA_11			(19)#define INT0_LO_EDMA_12			(20)#define INT0_LO_EDMA_13			(21)#define INT0_LO_EDMA_14			(22)#define INT0_LO_EDMA_15			(23)#define INT0_LO_EDMA_ERR		(24)#define INT0_LO_SCM			(25)#define INT0_LO_UART0			(26)#define INT0_LO_UART1			(27)#define INT0_LO_UART2			(28)#define INT0_LO_RSVD1			(29)#define INT0_LO_I2C			(30)#define INT0_LO_QSPI			(31)#define INT0_HI_DTMR0			(32)#define INT0_HI_DTMR1			(33)#define INT0_HI_DTMR2			(34)#define INT0_HI_DTMR3			(35)#define INT0_HI_FEC_TXF			(36)#define INT0_HI_FEC_TXB			(37)#define INT0_HI_FEC_UN			(38)#define INT0_HI_FEC_RL			(39)#define INT0_HI_FEC_RXF			(40)#define INT0_HI_FEC_RXB			(41)#define INT0_HI_FEC_MII			(42)#define INT0_HI_FEC_LC			(43)#define INT0_HI_FEC_HBERR		(44)#define INT0_HI_FEC_GRA			(45)#define INT0_HI_FEC_EBERR		(46)#define INT0_HI_FEC_BABT		(47)#define INT0_HI_FEC_BABR		(48)/* 49 - 61 Reserved */#define INT0_HI_SCM			(62)/* Bit definitions and macros for INTC_IPRH */#define INTC_IPRH_INT63			(0x80000000)#define INTC_IPRH_INT62			(0x40000000)#define INTC_IPRH_INT61			(0x20000000)#define INTC_IPRH_INT60			(0x10000000)#define INTC_IPRH_INT59			(0x08000000)